IP Library Granted Patent US 6,989,319
Granted Patent B1
US 6,989,319 · App. 10/718,707 · Granted Jan 24, 2006

Methods for forming nitrogen-rich regions in non-volatile semiconductor memory devices

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Quick Facts
Patent No.
US 6,989,319
App. No.
10/718,707
Granted
Jan 24, 2006
Kind
B1
Abstract

Methods and arrangements are provided for significantly reducing electron trapping in semiconductor devices having a polysilicon feature and an overlying dielectric layer. The methods and arrangements employ a nitrogen-rich region within the polysilicon feature near the interface to the overlying dielectric layer. The methods include selectively implanting nitrogen ions through at least a portion of the overlying dielectric layer and into the polysilicon feature to form an initial nitrogen concentration profile within the polysilicon feature. Next, the temperature within the polysilicon feature is raised to an adequately high temperature, for example using rapid thermal anneal (RTA) techniques, which cause the initial nitrogen concentration profile to change due to the migration of the majority of the nitrogen towards either the interface with the overlying dielectric layer or the interface with an underlying layer. Consequently, the polysilicon feature has a first nitrogen-rich region near the interface to the overlying dielectric layer and a second nitrogen-rich region near the interface to the underlying layer. The migration of nitrogen further forms a contiguous reduced-nitrogen region located between the first nitrogen-rich region and the second nitrogen-rich region. The contiguous reduced-nitrogen region has a lower concentration of nitrogen than does the first nitrogen-rich region and the second nitrogen-rich region. The first nitrogen-rich region has been found to reduce electron trapping within the polysilicon feature. Thus, for example, in a non-volatile memory device wherein the polysilicon feature is a floating gate, false programming of the memory device can be significantly avoided by reducing the number of trapped electrons in the floating gate.

Claims (27)

1. A method for forming a semiconductor device, the method comprising:

forming a first dielectric layer;

forming a first gate on the first dielectric layer;

forming a second dielectric layer on the first gate;

forming a silicon nitride film on the second dielectric layer; and then

forming a first nitrogen-rich region within the first gate and substantially adjacent to the first dielectric layer, and a second nitrogen-rich region within the first gate and substantially adjacent the second dielectric layer, wherein

the silicon nitride film is formed on the second dielectric layer prior to the step of forming the first nitrogen-rich region and the second nitrogen-rich region within the first gate.

2. The method as recited in claim 1 , wherein the step of forming a second dielectric layer on the first gate includes forming a first silicon dioxide film on the first gate.

3. The method as recited in claim 2 , wherein the step of forming a second dielectric layer on the first gate further includes forming a silicon nitride film on the first silicon dioxide film prior to the step of forming the first nitrogen-rich region and the second nitrogen-rich region within the first gate.

4. The method as recited in claim 3 , wherein the step of forming a second dielectric layer on the first gate further includes forming a second silicon dioxide film on the silicon nitride film prior to the step of the step of forming the first nitrogen-rich region and the second nitrogen-rich region within the first gate.

5. A method for forming a semiconductor device, the method comprising:

forming a first dielectric layer;

forming a first gate on the first dielectric layer;

forming a second dielectric layer on the first gate; and then

forming a first nitrogen-rich region within the first gate and substantially adjacent to the first dielectric layer, and a second nitrogen-rich region within the first gate and substantially adjacent the second dielectric layer, wherein the step of forming the first nitrogen-rich region and the second nitrogen-rich region within the first gate further comprises:

implanting nitrogen ions through the second dielectric layer and into the first gate, the implanted nitrogen ions forming a first nitrogen concentration profile within the first gate; and

causing the first nitrogen concentration profile to be altered to form a second nitrogen concentration profile within the first gate, the second nitrogen concentration profile comprising the first nitrogen-rich region, the second nitrogen-rich region and a contiguous reduced-nitrogen region located between the first nitrogen-rich region and the second nitrogen-rich region, the contiguous reduced-nitrogen region having a lower concentration of nitrogen than the first nitrogen-rich region and the second nitrogen-rich region.

6. The method as recited in claim 5 , wherein the step of causing the first nitrogen concentration profile to be altered further comprises causing the first nitrogen-rich region to include between about 0.01% and about 1% atomic percentage of nitrogen.

7. The method as recited in claim 6 , wherein the step of the step of causing the first nitrogen concentration profile to be altered further comprises causing the second nitrogen-rich region to include between about 0.01% and about 1% atomic percentage of nitrogen.

8. The method as recited in claim 5 , wherein the step of causing the first nitrogen concentration profile to be altered to form the second nitrogen concentration profile within the first gate further comprises causing the lower concentration of nitrogen in the contiguous reduced-nitrogen region to include less than about 0.001% atomic percentage of nitrogen.

9. The method as recited in claim 5 , wherein the step of implanting nitrogen ions through the second dielectric layer and into the first gate uses an ion implantation energy of between about 10 and about 30 KeV to provide a dosage of between about 1×10 14 and about 1×10 16 nitrogen ions/cm 2 .

10. The method as recited in claim 5 , wherein the step of causing the first nitrogen concentration profile to be altered to form a second nitrogen concentration profile within the first gate further includes applying thermal energy to the first gate.

11. The method as recited in claim 10 , wherein the step of applying thermal energy to the first gate causes an internal temperature within the first gate of between about 900 and about 1100° C.

12. A method for nitrogen doping a polysilicon layer, the method comprising:

forming a polysilicon layer in a semiconductor device, the polysilicon layer sharing a first interface with an underlying dielectric layer and a second interface with an overlying dielectric layer;

implanting nitrogen through the overlying dielectric layer and substantially into a polysilicon layer; and

heating the polysilicon layer to cause the implanted nitrogen to form a first nitrogen-rich region substantially adjacent to the underlying dielectric layer and a substantially separate second nitrogen-rich region substantially adjacent the overlying dielectric layer, thereby leaving a reduced-nitrogen region located within the polysilicon layer between the first nitrogen-rich region and the second nitrogen-rich region, wherein the reduced-nitrogen region always has a lower concentration of nitrogen than the first nitrogen-rich region and the second nitrogen-rich region.

Assignments (9)
CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST. Recorded Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 14, 2016
From: CYPRESS SEMICONDUCTOR CORPORATION
To: MONTEREY RESEARCH, LLC
Reel/Frame 040911/0238 →
PARTIAL RELEASE OF SECURITY INTEREST IN PATENTS Recorded Aug 11, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 039708/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 30, 2015
From: SPANSION, LLC
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 036037/0716 →
SECURITY INTEREST Recorded Mar 21, 2015
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 035240/0429 →
RELEASE OF SECURITY INTEREST Recorded Mar 13, 2015
From: BARCLAYS BANK PLC
To: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY LLC
Reel/Frame 035201/0159 →
SECURITY AGREEMENT Recorded Jun 4, 2010
From: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY INC.; SPANSION TECHNOLOGY LLC
To: BARCLAYS BANK PLC
Reel/Frame 024522/0338 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 27, 2007
From: SPANSION INC.
To: SPANSION LLC
Reel/Frame 019069/0028 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 19, 2007
From: ADVANCED MICRO DEVICES, INC.
To: SPANSION INC.
Reel/Frame 019028/0623 →