Method of forming trench in semiconductor device
View Patent ↗The present invention is provided to form a trench in a semiconductor device, wherein by performing an ion implanting process to an area of a semiconductor substrate in which the trench would be formed to cause lattice defects in the area before forming the trench, an etching speed of the area is increased in subsequent trench forming processes. As a result, it is possible to prevent micro trenches from being formed in edge portions of patterns and to suppress a micro loading effect to be generated depending upon pattern sizes.
1. A method of forming a trench in a semiconductor device, comprising:
(a) a step of depositing a first pad film and a second pad film on a semiconductor substrate;
(b) a step of patterning the first pad film and the second pad film;
(c) a step of forming spacers on inner side walls of the patterned first and second pad films;
(d) a step of performing a first ion implanting process to the semiconductor substrate exposed between the spacers;
(e) a step of performing an etching process to decrease thicknesses of the spacers, thereby increasing a line-width of a trench to be formed in subsequent processes;
(f) a step of performing a second ion implanting process to the semiconductor substrate; and
(g) a step of etching an area of the semiconductor substrate in which lattice defects are caused through the first and second ion implanting processes, thereby forming the trench.
2. A method of forming a trench in a semiconductor device according to claim 1 , wherein the first and second ion implanting processes use an inert gas in the periodic table.
3. A method of forming a trench in a semiconductor device according to claim 2 , wherein the inert gas is selected from the group consisting of He, Ne, Ar, Kr, and Xe.
4. A method of forming a trench in a semiconductor device according to claim 1 , wherein the first ion implanting process is performed with an ion dose in a range of 1.0×10 10 ions/cm 2 to 1.0×10 18 ions/cm 2 and an ion implanting energy in a range of 3 KeV to 60 KeV.
5. A method of forming a trench in a semiconductor device according to claim 1 , wherein ions implanted through the first ion implanting process in the step of (d) are distributed in the semiconductor substrate with a range of about 1000 Å to 4000 Å.
6. A method of forming a trench in a semiconductor device according to claim 1 , wherein the second ion implanting process is performed with an ion dose in a range of 1.0×10 10 ions/cm 2 to 1.0×10 18 ions/cm 2 and an ion implanting energy in a range of 3 KeV to 55 KeV.
7. A method of forming a trench in a semiconductor device according to claim 1 , wherein ions implanted through the second ion implanting process in the step of (f) are distributed in the semiconductor substrate with a range of about 300 Å to 3000 Å.
8. A method of forming a trench in a semiconductor device according to claim 1 , wherein the step of (a) further comprises a step of depositing an oxide film on the second pad film.
9. A method of forming a trench in a semiconductor device, comprising:
(a) a step of depositing a first pad film and a second pad film on a semiconductor substrate;
(b) a step of patterning the first pad film and the second pad film;
(c) a step of forming spacers on inner side walls of the patterned first and second pad films;
(d) a step of performing an etching process to decrease thickness of the spacers, thereby increasing a line-width of a trench to be formed in subsequent processes;
(e) a step of performing an ion implanting process to the semiconductor substrate exposed between the spacers;
(f) a step of etching an area of the semiconductor substrate in which lattice defects are caused through the ion implanting processes, thereby forming the trench.
10. A method of forming a trench in a semiconductor device according to claim 9 , wherein the ion implanting process uses an inert gas in the periodic table.
11. A method of forming a trench in a semiconductor device according to claim 10 , wherein the inert gas is selected from the group consisting of He, Ne, Ar, Kr, and Xe.
12. A method of forming a trench in a semiconductor device according to claim 9 , wherein the ion implanting process is performed with an ion dose in a range of 1.0×10 10 ions/cm 2 to 1.0×10 18 ions/cm 2 and an ion implanting energy in a range of 3 KeV to 60 KeV.
13. A method of forming a trench in a semiconductor device according to claim 9 , wherein the ion implanting process is performed with an ion dose in a range of 1.0×10 10 ions/cm 2 to 1.0×10 18 ions/cm 2 and an ion implanting energy in a range of 3 KeV to 55 KeV.
14. A method of forming a trench in a semiconductor device according to claim 9 , wherein ions implanted through the ion implanting process are distributed in the semiconductor substrate with a range of about 300 Å to 3000 Å.
15. A method of forming a trench in a semiconductor device according to claim 9 , wherein the step of (a) further comprises a step of depositing an oxide film on the second pad film.