IP Library Granted Patent US 7,037,822
Granted Patent B2
US 7,037,822 · App. 10/731,480 · Granted May 2, 2006

Method of forming metal line in semiconductor device

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Quick Facts
Patent No.
US 7,037,822
App. No.
10/731,480
Granted
May 2, 2006
Kind
B2
Abstract

Disclosed in a method of forming a metal line in a semiconductor device. The method includes the steps of sequentially forming a first etch stop film, a second interlayer insulating film and a BARC film on a first interlayer insulating film into which a metal line is buried, forming a photoresist pattern defining a trench in a given region of the BARC film, performing an etch process up to the second interlayer insulating film using the photoresist pattern as an etch mask to form a trench, removing the photoresist pattern and the BARC film by means of a first wet etch process, etching the first etch stop film by means of a second wet etch process using the second interlayer insulating film an as etch mask, and cleaning the resulting entire surface by means of a third wet etch process. As such, by removing the photoresist pattern, the BARC film and the etch stop film through the wet etch process, it is possible to reduce the amount of polymer generated in the process for forming the via hole and the metal line trench.

Claims (18)

1. A method of forming a metal line in a semiconductor device, comprising the steps of:

sequentially forming a first etch stop film, a second interlayer insulating film, a second etch stop film and a third interlayer insulating film on a first interlayer insulating film into which a metal line is buried;

forming a first photoresist pattern defining a via hole in a given region of the third interlayer insulating film;

performing an etch process using the first photoresist pattern as an etch mask up to the first etch stop film to form the via hole, and then removing the first photoresist pattern;

forming a BARC film on the resulting surface and then forming a second photoresist pattern defining the metal line in another given region of the BARC film;

performing an etch process using the second photoresist pattern as an etch mask up to the second etch stop film to form a metal line trench, and then removing the second photoresist pattern and the BARC film by means of a first wet etch process;

etching the first etch stop film by means of a second wet etch process using the second interlayer insulating film as an etch mask; and

cleaning the resulting entire surface by means of a third wet etch process.

2. The method as claimed in claim 1 , wherein the first wet etch process is performed using an aqueous solution in which sulfuric acid (H 2 SO 4 ) and hydrogen peroxide (H 2 O 2 ) are mixed in the ratio of one of 2:1, 4:1 and 6:1 at a bath temperature of about 100° C. to 140° C. for about 2 to 10 minutes.

3. The method as claimed in claim 1 , wherein the second wet etch process is performed using an aqueous solution in which HNO 3 of 60 to 90% is mixed at a bath temperature of about 140° C. to 180° C. for about 10 to 60 minutes.

4. The method as claimed in claim 1 , wherein the third wet etch process is performed using an aqueous solution in which HF and DI water are mixed in the ratio of one of 200:1, 19:1, 500:1 and 600:1 at a bath temperature of a room temperature for about 10 to 60 minutes.

5. A method of forming a metal line in a semiconductor device, comprising the steps of:

sequentially forming a first etch stop film, a second interlayer insulating film and a BARC film on a first interlayer insulating film into which a metal line is buried;

forming a photoresist pattern defining a trench in a given region of the BARC film;

performing an etch process up to the second interlayer insulating film using the photoresist pattern as an etch mask to form a trench;

removing the photoresist pattern and the BARC film by means of a first wet etch process;

etching the first etch stop film by means of a second wet etch process using the second interlayer insulating film an as etch mask; and

cleaning the resulting entire surface by means of a third wet etch process.

Assignments (13)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
THE SUBMISSION IS TO CORRECT AN ERROR MADE IN A PREVIOUSLY RECORDED DOCUMENT ON REEL/FRAME 016216/0649 RECORDED ON 01/10/2005 THAT ERRONEOUSLY AFFECTS THE IDENTIFIED PATENT NO. 7037822. AN AFFIDAVIT IS BEING FILED HEREWITH. Recorded May 29, 2013
From: MAGNACHIP SEMICONDUCTOR, LTD.
To: HYNIX SEMICONDUCTOR, INC.
Reel/Frame 030508/0646 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 11, 2011
From: HYNIX SEMICONDUCTOR INC.
To: NUMONYX B.V.
Reel/Frame 027217/0862 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 11, 2011
From: NUMONYX B.V.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 027217/0837 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 6, 2006
From: HYNIX SEMICONDUCTOR INC.
To: HYNIX SEMICONDUCTOR INC.; STMICROELECTRONICS S.R.L.
Reel/Frame 018207/0057 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 10, 2005
From: HYNIX SEMICONDUCTOR, INC.
To: MAGNACHIP SEMICONDUCTOR, LTD.
Reel/Frame 016216/0649 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 10, 2003
From: CHO, IHL HYUN
To: HYNIX SEMICONDUCTOR INC.
Reel/Frame 014787/0179 →