Method of manufacturing high voltage transistor in flash memory device

1. A method of manufacturing a high voltage transistor in a flash memory device, comprising:

performing a first ion implantation process for controlling a threshold voltage of a high voltage transistor for a semiconductor substrate and for preventing a punch leakage at a bottom of an isolation film;

forming a gate oxide film for a high voltage device on the semiconductor substrate;

sequentially forming a polysilicon film and a pad nitride film on the resulting structure including the gate oxide film;

forming a shallow trench that extends into the semiconductor substrate by sequentially etching a portion of the pad nitride film, the first polysilicon film and the semiconductor substrate;

filling the shallow trench with an insulating film to form the isolation film;

removing the pad nitride film to expose the polysilicon film; and

performing a second ion implantation process to form a source/drain junction of the high voltage transistor.

2. The method as claimed in claim 1 , wherein the first ion implantation process for controlling the threshold voltage of the high voltage transistor is performed with a high energy in the range of about 60 KeV to 80 KeV so as to prevent punch leakage at a bottom of the isolation film of the shallow trench.

3. The method as claimed in claim 2 , wherein the first ion implantation process for controlling the threshold voltage of the high voltage transistor is performed with a dose in the range of about 8.0E11 atoms/cm 2 to 1.5E12 atoms/cm 2.

4. The method as claimed in claim 1 , wherein the shallow trench is formed with a depth in the range of about 1000 Å to 2000 Å so as to prevent punch leakage current at a bottom of the isolation film.

5. The method as claimed in claim 1 , wherein the second ion implantation process for forming the source/drain junction of the high voltage transistor is performed with a low energy in the range of about 30 KeV to 50 KeV in order to further prevent punch leakage of the isolation film due to the shallow trench.

6. The method as claimed in claim 5 , wherein the second ion implantation process for forming the source/drain junction of the high voltage transistor is performed with a low dose in the range of about 3.0E12 atoms/cm 2 to 1E13 atoms/cm 2 so as to satisfy a high drain junction breakdown voltage.

7. The method as claimed in claim 1 , further comprising depositing a polysilicon film on the gate oxide film for the high voltage device before the pad nitride film is formed.

8. A method of manufacturing a transistor in a flash memory device, comprising:

performing a first ion implantation process for controlling a threshold voltage of a high voltage transistor and for preventing a punch leakage at a bottom of an isolation film;

forming a first gate oxide film for the high voltage transistor and a second gate oxide film for a low voltage transistor on the semiconductor substrate;

sequentially forming a polysilicon film and a pad nitride film on an entire structure including the first gate oxide film and the second gate oxide film;

forming a shallow trench that extends into the semiconductor substrate by sequentially etching a portion of the pad nitride film, the first polysilicon film and the semiconductor substrate;

forming the isolation film by burying the shallow trench with an insulating film;

removing the pad nitride film to expose the polysilicon film; and

performing a second ion implantation process to form a source/drain.

9. The method as claimed in claim 8 , wherein the first ion implantation process for controlling the threshold voltage of the high voltage transistor is performed with a high energy in the range of about 60 KeV to 80 KeV so as to prevent the punch leakage at the bottom of the isolation film of the shallow trench.

10. The method as claimed in claim 9 , wherein the first ion implantation process for controlling the threshold voltage of the high voltage transistor is performed with a dose in the range of about 8.0E11 atoms/cm 2 to 1.5E12 atoms/cm 2.

11. The method as claimed in claim 8 , wherein the shallow trench is formed with a depth in the range of about 1000 Å to 2000 Å so as to prevent punch leakage current at a bottom of the isolation film.

12. The method as claimed in claim 8 , wherein the second ion implantation process for forming the source/drain junction of the high voltage transistor is performed with a low energy in the range of about 30 KeV to 50 KeV in order to prevent a punch leakage of the isolation film due to the shallow trench.

13. The method as claimed in claim 12 , wherein the second ion implantation process for forming the source/drain junction of the high voltage transistor is performed with a low dose in the range of about 3.0E12 atoms/cm 2 to 1E13 atoms/cm 2 so as to satisfy a high drain junction breakdown voltage.