Cell array block of FeRAM, and FeRAM using cell array
View Patent ↗The present invention discloses a cell array block of a ferroelectric random access memory (FeRAM) and an FeRAM using the same. In the multi-bit line structure cell array block of the FeRAM having a sub bit line and a main bit line, and including a plurality of sub cell arrays for inducing a sensing voltage of the main bit line by converting a sensing voltage of the sub bit line into current, in order to overcome different data properties of the whole sub cell arrays due to delay time differences by positions of the sub cell arrays, a different size of sensing loads are selectively transmitted to the main bit line according to the positions of the operated sub cell arrays, or a different size of ferroelectric capacitors are used in a memory cell according to the positions of the sub cell arrays. As a result, the cell data properties of the whole cell array block are equalized for even distribution.
1. A cell array block of a ferroelectric random access memory, comprising:
a cell array unit including a plurality of sub cell arrays wherein a sensing voltage of a main bitline is induced depending on the amount of current leaked from the main bitline by a sensing voltage of a sub bitline;
a main bit line pull-up control unit for pulling up the main bit line in response to a main bit line pull-up control signal in a precharge mode;
a main bit line sensing load unit for controlling a sensing load of the main bit line in consideration of a position of the sub cell array in response to a main bit line load control signal; and
a column select switch unit for selectively outputting the sensing voltage of the main bit line to a common data bus in response to a column select signal.
2. The cell array block of claim 1 , wherein the main bit line sensing load unit comprises a plurality of switching devices selectively turned on/off in response to the main bit line load control signal, for varying the sensing load of the main bit line.
3. The cell array block of claim 2 , wherein the plurality of switching devices have different channel resistance.
4. A cell array block of a ferroelectric random access memory, comprising:
a cell array unit including a plurality of sub cell arrays wherein a sensing voltage of a main bitline is induced depending on the amount of current leaked from the main bitline by a sensing voltage of a sub bitline according to a data value of a memory cell having ferroelectric capacitors;
a main bit line pull-up control unit for pulling up the main bit line in response to a main bit line pull-up control signal in a precharge mode;
a main bit line sensing load unit for applying a sensing load to the main bit line in response to a main bit line load control signal; and
a column select switch unit for selectively outputting the sensing voltage of the main bit line to a common data bus in response to a column select signal,
wherein the ferroelectric capacitors have different capacitances according to positions of the plurality of sub cell arrays.
5. A cell array block of a ferroelectric random access memory, comprising:
a cell array unit including a plurality of sub cell arrays wherein a sensing voltage of a main bitline is induced depending on the amount of current leaked from the main bitline by a sensing voltage of a sub bitline according to a data value of a memory cell having ferroelectric capacitors;
a main bit line pull-up control unit for pulling up the main bit line in response to a main bit line pull-up control signal in a precharge mode;
a main bit line sensing load unit for controlling a sensing load of the main bit line in consideration of a position of the sub cell array in response to a main bit line load control signal; and
a column select switch unit for selectively outputting the sensing voltage of the main bit line to a common data bus in response to a column select signal,
wherein the ferroelectric capacitors have different capacitances according to the positions of the plurality of sub cell arrays.
6. The cell array block of claim 5 , wherein the main bit line sensing load unit comprises a plurality of switching devices selectively turned on/off in response to the main bit line load control signal, for varying the sensing load of the main bit line.
7. The cell array block of claim 6 , wherein the plurality of switching devices have different channel resistance values.
8. A ferroelectric random access memory, comprising:
a plurality of cell array blocks including a plurality of sub cell arrays wherein a sensing voltage of a main bitline is induced depending on the amount of current leaked from the main bitline by a sensing voltage of a sub bitline;
a common data bus shared by the plurality of cell array blocks, for transmitting read data and write data for the cell array blocks; and
a timing data register array unit connected to the common data bus, for sensing the read data and outputting the write data to the common data bus,
wherein a sensing load of the main bit line is variably controlled according to a position of the operated sub cell array.
9. The ferroelectric random access memory of claim 8 , wherein the plurality of cell array blocks each respectively comprise:
a cell array unit including the plurality of sub cell arrays;
a main bit line pull-up control unit for pulling up the main bit line in response to a main bit line pull-up control signal in a precharge mode;
a main bit line sensing load unit for control ling a sensing load of the main bit line in consideration of a position of the sub cell array in response to a main bit line load control signal; and
a column select switch unit for selectively outputting the sensing voltage of the main bit line to a common data bus in response to a column select signal.
10. The ferroelectric random access memory of claim 9 , wherein the main bit line sensing load unit variably controls the sensing load of the main bit line according to distances between the operated sub cell array and the timing data register array unit.
11. The ferroelectric random access memory of claim 10 , wherein the main bit line sensing load unit comprises a plurality of switching devices selectively turned on/off in response to the main bit line load control signal, for varying the sensing load of the main bit line.
12. The ferroelectric random access memory of claim 11 , wherein the plurality of switching devices have different channel resistance values.
13. A ferroelectric random access memory, comprising:
a plurality of cell array blocks including a plurality of sub cell arrays wherein a sensing voltage of a main bitline is induced depending on the amount of current leaked from the main bitline by a sensing voltage of a sub bitline;
a common data bus shared by the plurality of cell array blocks, for transmitting read data and write data for the cell array blocks; and
a timing data register array unit connected to the common data bus, for sensing the read data and outputting the write data to the common data bus,
wherein the plurality of sub cell arrays have different capacitances of ferroelectric capacitors in a memory cell for storing data according to their positions.
14. The ferroelectric random access memory of claim 13 , wherein the plurality of sub cell arrays have different capacitances according to distances from the timing data register array unit.
15. A ferroelectric random access memory, comprising:
a plurality of cell array blocks including a plurality of sub cell arrays wherein a sensing voltage of a main bitline is induced depending on the amount of current leaked from the main bitline by a sensing voltage of a sub bitline;
a common data bus shared by the plurality of cell array blocks, for transmitting read data and write data for the cell array blocks; and
a timing data register array unit connected to the common data bus, for sensing the read data and outputting the write data to the common data bus,
wherein a sensing load of the main bit line is variably controlled and the plurality of cell array blocks have different capacitances of ferroelectric capacitors according to positions of the plurality of sub cell arrays.
16. The ferroelectric random access memory of claim 15 , wherein the plurality of cell array blocks each respectively comprise:
a cell array unit including the plurality of sub cell arrays having different capacitances in a memory cell according to their positions;
a main bit line pull-up control unit for pulling up the main bit line in response to a main bit line pull-up control signal in a precharge mode;
a main bit line sensing load unit for controlling a sensing load of the main bit line in consideration of the position of the sub cell array in response to a main bit line load control signal; and
a column select switch unit for selectively outputting the sensing voltage of the main bit line to the common data bus in response to a column select signal.
17. The ferroelectric random access memory of claim 16 , wherein the main bit line sensing load unit comprises a plurality of switching devices selectively turned on/off in response to the main bit line load control signal, for varying the sensing load of the main bit line.
18. The ferroelectric random access memory of claim 17 , wherein the plurality of switching devices have different channel resistance values.