Method and device for programming cells in a memory array in a narrow distribution
View Patent ↗Accurately programming a memory cell. A voltage is applied to a drain of the memory cell to program the cell. After applying the voltage, the cell is verified as to whether it is programmed to a desired level. The magnitude of the programming voltage is increased and applied to the drain, and the memory cell is re-verified for the desired level. This is repeated until the memory cell is programmed to the desired level. Additional memory cells are programmed in this fashion in order to program multiple memory cells in a narrow distribution around the desired level. The programming can be done one memory cell at a time or many cells can be programmed in parallel. Further a ramped programming voltage can applied to the gate of the memory cell(s), such that the ramped voltage to the gate and the ramped voltage to the drain both program the memory cell.
1. A method for accurately programming a memory cell, comprising:
a) applying a first voltage to a drain and a second voltage to a gate of said memory cell to program said memory cell;
b) verifying whether said memory cell is programmed to a desired level after applying said voltage; and
c) increasing the respective magnitudes of said first voltage to said drain and said second voltage to said gate and repeating said a) and b) until said memory cell is programmed to said desired level, wherein said memory cell is programmed accurately to said desired level.
2. The method of claim 1 , further comprising applying a voltage to said gate of said memory cell to verify whether said memory cell is programmed to said desired level.
3. The method of claim 1 , wherein said c) comprises increasing said magnitude of said first voltage in a non-linear step size.
4. The method of claim 1 , wherein said c) comprises increasing said magnitude of said first voltage in a substantially linear step size.
5. The method of claim 1 , wherein said desired level is one of at least three programming levels.
6. The method of claim 1 , wherein said desired level is one of at least four programming levels.
7. A method for programming a multi-level cell (MLC) memory array in a narrow distribution, comprising:
a) applying a first voltage to a drain of a first memory cell;
b) determining whether said first memory cell is programmed to a desired level after applying said first voltage;
c) increasing said first voltage and repeating said a) and b) until the first memory cell is programmed to said desired level, wherein said increasing said first voltage comprises a non-linear pattern comprising progressively smaller step sizes followed by progressively larger step sizes; and
d) performing said a)–c) for at least one additional memory cell in said memory array in order to program a plurality of memory cells in a narrow distribution around said desired level.
8. The method of claim 7 , wherein said first memory cell is programmed before programming said at least one additional memory cell.
9. The method of claim 7 , wherein said first memory cell is programmed in parallel with said at least one additional memory cell.
10. The method of claim 7 , further comprising:
e) programming a second plurality of cells in said memory array to a second level by performing said a) through said d) until each memory cell of said second plurality of memory cells is programmed to said second level, and wherein said second level is different from the desired level in said b) through said d).
11. The method of claim 7 , further comprising applying a substantially constant voltage to a gate of said first memory cell during said a)–c), wherein said voltage applied to said gate is also used in said b) to verify whether said memory cell is programmed to said desired level.
12. The method of claim 7 , wherein:
said a) further comprises applying a voltage to a gate of said first memory cell; and
said c) further comprises increasing said voltage to said gate of said first memory cell.
13. A multi-level cell memory device comprising:
an array of memory cells suitable for multi-level programming;
a first circuit that is operable to apply a first programming voltage to drains and a second programming voltage to gates of said plurality of memory cells;
a second circuit that is operable to verify whether said plurality of memory cells are programmed to a desired level of a plurality of levels; and
a third circuit that is operable to increase said first programming voltage to said drains and is further operable to increase said second programming voltage to said gates if said verify indicates additional programming is required to reach said desired level.
14. The multi-level cell memory device of claim 13 , wherein said third circuit is further operable to increase said first programming voltage to said drains in a non-linear fashion.
15. The multi-level cell memory device of claim 14 , wherein said third circuit is further operable to increase said second programming voltage to said gates of said memory cells in a linear fashion.