Method of reading memory device in page mode and row decoder control circuit using the same
View Patent ↗The Disclosed is a method of reading a memory device in a page mode. The method includes the steps of inputting a row address for selecting the word line, enabling a corresponding word line by the row address, and reading/restoring the level of the cell node connected to the enabled word line, and disabling the enabled word line and sequentially enabling bit line sense amplifiers connected to the disabled word line to perform a read operation, wherein the disabling of the selected word line is performed after a lapse of a certain time period as much as data of a first cell node can be restored. Therefore, it is possible to reduce current consumption in a read operation of a page mode.
1. A method of reading a memory device in a page mode, wherein a single word line is enabled to sense levels of a plurality of cell nodes connected thereto, comprising the steps of:
(a) inputting a row address for selecting the word line;
(b) enabling a corresponding word line by the row address, and reading/restoring the level of the cell node connected to the enabled word line; and
(c) disabling the enabled word line and sequentially enabling bit line sense amplifiers connected to the disabled word line to perform a read operation,
wherein the disabling of the selected word line is performed after a lapse of a certain time period as much as data of a first cell node can be restored.
2. The method as claimed in claim 1 , wherein the disabling of the selected word line is performed using a precharge control signal (pcg).
3. The method as claimed in claim 2 , wherein the precharge control signal (pcg) is generated by using a given delay sense signal to generate a pulse.
4. The method as claimed in claim 3 , wherein the precharge control signal (pcg) is generated by performing a NAND operation for the given delay sense signal and an address transition detector signal generated by a page address.
5. A row decoder control circuit for controlling a row decoder, which is controlled by an internal address, a row active signal and a precharge control signal, in a page mode wherein a single word line is enabled to sense levels of a plurality of cell nodes connected thereto, comprising a pulse output unit for outputting a given delay sense signal inputted thereto as a pulse and then inputting the pulse as the precharge control signal,
wherein, after the word line is enabled by a row address, the precharge control signal is outputted after a lapse of a certain time period as much as the data of a first cell node can be restored, and the enabled word line is then disabled in response to the outputted precharge control signal.
6. The row decoder control circuit as claimed in claim 5 , wherein the pulse output unit comprises:
a first inverter for inverting the given delay sense signal;
a delay unit connected to the inverter, for delaying the inverted given delay sense signal;
a NAND device for performing a NAND operation for the given delay sense signal and a signal passed through the delay unit; and
a second inverter connected to the output of the NAND device.
7. A row decoder control circuit for controlling a row decoder, which is controlled by an internal address, a row active signal and a precharge control signal, in a page mode wherein a single word line is enabled to sense levels of a plurality of cell nodes connected thereto, comprising a pulse output unit for performing a NAND operation for a given delay sense signal and an address transition detector signal of a page address to output the signals as pulses, and inputting the pulses as a precharge control signal,
wherein the address transition detector signal is generated by a page address for reading at least second cell node within the same row address, and the enable word line is disabled in response to the output precharge control signal.