Data input/output buffer and semiconductor memory device using the same
View Patent ↗Provided is a data input/output buffer and a semiconductor memory device using the same. A transistor of a switching means or a logical element out of devices constituting a data input/output buffer, to which a data signal is inputted most rapidly, is implemented using a low voltage-driven device whose threshold voltage is low. It is therefore possible to improve reliability of a circuit by exactly determining the level of a data signal even if the data signal is inputted as a level that is lowered as much as a threshold voltage.
1. A data input/output buffer comprising:
a PMOS transistor driven according to the data signal which is directly inputted to the PMOS transistor from a peripheral circuit and connected to a power supply voltage terminal;
a low voltage-driven NMOS transistor driven according to the data signal which is directly inputted to the low voltage-driven NMOS transistor from the peripheral circuit and connected to the PMOS transistor, wherein the low voltage-driven NMOS transistor having a threshold voltage of 0V;
a NMOS transistor connected between the low voltage-driven NMOS transistor and a ground voltage terminal, wherein the NMOS transistor is turned on according to an output enable signal; and
a latch unit for inverting and restoring a signal received via the PMOS transistor or the low voltage-driven NMOS transistor.
2. A data input/output buffer comprising:
a first logical element driven according to a data signal directly inputted to the first logical element from a peripheral circuit, the first logical element having a PMOS transistor and a low voltage-driven NMOS transistor;
a second logical element for inverting and restoring a signal received via the PMOS transistor or the low voltage-driven NMOS transistor; and
a NMOS transistor that is connected between the low voltage-driven NMOS transistor and a ground voltage terminal with the switching element being turned on according to an output enable signal,
wherein the low voltage-driven NMOS transistor having a threshold voltage of 0V.
3. A semiconductor memory device, comprising:
a memory cell array;
a row decoder for selecting a given page of the memory cell array according to a row address signal;
a page buffer for storing data stored at the page selected by the row decoder;
a column decoder for generating a bit line select signal according to a column address signal;
a column multiplexer for selecting and outputting any one of the data stored at the page buffer according to the bit line select signal; and
a data input/output buffer for storing the data selected by the column multiplexer and transferring the data to a data line, wherein the data input/output buffer comprises a PMOS transistor driven according to the data signal directly inputted to the PMOS transistor from the column multiplexer and connected to a power supply voltage terminal;
a low voltage-driven NMOS transistor driven according to the data signal directly inputted to the low voltage-driven NMOS transistor from the column multiplexer and connected to the PMOS transistor, wherein the low voltage-driven NMOS transistor having a threshold voltage of 0V;
a NMOS transistor connected between the low voltage-driven NMOS transistor and a ground voltage terminal, wherein the NMOS transistor is turned on according to an output enable signal; and
a latch unit for inverting and restoring a signal received via the PMOS transistor or the low voltage-driven NMOS transistor.