Semiconductor memory device for preventing skew and timing error of output data
View Patent ↗A semiconductor memory device includes at least memory cell block which has a plurality of memory cells and outputs a plurality of data signals in response to a read command signal; a data latching unit for latching and outputting the plurality of data signals in response to a data output control signal generated in response to the read command signal; a data selection unit for selecting a data output mode from the plurality of data output modes in response to a data selection signal and for outputting data corresponding to the selected data output mode; and a data output control unit for outputting a data selection signal to the data selection unit in response to the data output control signal.
1. A semiconductor memory device, comprising:
at least one memory cell block which has a plurality of memory cells and outputs a plurality of data signals according to a read command signal;
a data latching unit for latching the plurality of data signals to thereby output the plurality of data signals when a data output control signal, generated based on the read command signal, is activated;
a data selection unit for selecting a predetermined number of data signals among the plurality of data signals according to a data selection signal; and
a data output control unit for receiving a plurality of address signals to thereby generate the data selection signal based on the data output control signal.
2. The semiconductor memory device as recited in claim 1 , further comprising a command execution controlling unit for generating the data output control signal according to the read command signal.
3. The semiconductor memory device as recited in claim 1 , wherein the data output control unit includes a plurality of data selection signal generators, each including:
a first control signal latching unit for latching and outputting a first control signal according to the data output control signal; and
a second control signal latching unit for latching and outputting an output of the first control signal latching unit according to the data output control signal to thereby generate the data selection signal.
4. The semiconductor memory device as recited in claim 3 , wherein the first control signal is one of the plurality of address signals.
5. The semiconductor memory device as recited in claim 3 , wherein the first control signal latching unit includes:
a first transferring gate which is turned on for transferring the first control signal in response to the data output control signal; and
a first latch for latching the first control signal from the first transferring gate.
6. The semiconductor memory device as recited in claim 5 , wherein the second control signal latching unit includes:
a second transferring gate which is turned on for transferring the output from the first control signal latching unit in response to the data output control signal; and
a second latch for latching an output of the second transferring gate to thereby output the output of the second transferring gate as the data selection signal.