Methods of forming metal lines in semiconductor devices
View Patent ↗Methods of forming metal lines in semiconductor devices are disclosed. One example method may include forming lower metal lines and forming an insulation layer on the lower metal lines; etching said insulation layer to a depth; and depositing a material for upper metal lines on the entire surface of said insulation layer and planarizing the material for the upper metal lines to form said upper metal lines. The example method may also include exposing the lower metal lines by etching said upper metal lines and the insulation layer and depositing a material for contact plugs on the entire surfaces of said upper metal lines and said insulation layer and planarizing the material for said contact plugs to form the contact plugs.
1. A method of forming metal lines in a semiconductor device, the method comprising:
forming lower metal lines and forming an insulation layer on the lower metal lines;
partially etching said insulation layer to a depth which upper metal lines are to be formed;
depositing a material for the upper metal lines on the entire surface of said insulation layer and planarizing the material for the upper metal lines to form said upper metal lines;
exposing the lower metal lines by forming a photoresist pattern on the entire surface of the resultant structure, performing a dry etching process on the upper metal lines and said insulation layer using an etchant having about 1:1 selectivity between said upper metal line and said insulation layer until said lower metal lines are exposed to form contact holes through said upper metal lines and the insulation layer, and removing said photoresist pattern; and
depositing a material for contact plugs on entire exposed surfaces of said upper metal lines, said insulation layer, and said contact holes, and planarizing the material for said contact plugs to form the contact plugs, wherein the material for contact plugs is deposited in the contact hole while the upper surfaces of the upper metal lines are completely exposed, thereby placing the material for the contact plugs in contact with exposed surfaces of said upper metal lines and said insulation layer, and forming an electrical connection between the lower and the upper metal lines via the contact plugs.
2. A method as defined by claim 1 , wherein said material for said upper metal lines is selected from the group consisting of W, CVD Al, CVD TiN and TaN.
3. A method as defined by claim 2 , wherein said material for said upper metal lines comprises CVD TiN.
4. A method as defined by claim 1 , wherein said material for said contact plugs is selected from the group consisting of CVD TaN, TiN, W and CVD Al.
5. A method as defined by claim 4 , wherein said material for said upper metal lines is selected from the group consisting of W, CVD Al, CVD TiN and TaN.
6. A method as defined by claim 5 , wherein said material for said upper metal lines comprises CVD TiN, and said material for said contact plugs comprises W.
7. A method as defined by claim 4 , wherein said material for said contact plugs comprises W.
8. A method as defined by claim 1 , wherein forming the insulation layer comprises depositing the insulation layer, then planarizing the insulation layer by a chemical mechanical polishing (“CMP”) process.
9. A method as defined by claim 1 , wherein planarizing the material for the upper metal lines comprises a chemical mechanical polishing (“CMP”) process.
10. A method of forming metal lines in a semiconductor device, the method comprising:
forming lower metal lines and forming an insulation layer on the lower metal lines;
partially etching said insulation layer to a depth which upper metal lines are to be formed;
depositing a material for the upper metal lines on the entire surface of said insulation layer and planarizing the material for the upper metal lines to form said upper metal lines;
exposing the lower metal lines by:
forming a photoresist pattern on the entire surface of the resultant structure;
performing a dry etching process on said upper metal lines and said insulation layer using an etchant having a higher selectivity for said insulation layer than that for said upper metal lines until the lower metal lines are exposed; and
removing said photoresist pattern; and
depositing a material for contact plugs on entire exposed surfaces of said upper metal lines, said insulation layer, and said contact holes, and planarizing the material for said contact plugs to form the contact plugs, wherein the material for contact plugs is deposited in the contact hole while the upper surfaces of the upper metal lines are completely exposed, thereby placing the material for the contact plugs in contact with exposed surfaces of said upper metal lines and said insulation layer, and forming an electrical connection between the lower and the upper metal lines via the contact plugs.
11. A method as defined by claim 10 , wherein said material for said upper metal lines is selected from the group consisting of W, CVD Al, CVD TiN and TaN.
12. A method as defined by claim 11 , wherein said material for said upper metal lines comprises CVD TiN.
13. A method as defined by claim 11 , wherein said material for said contact plugs is selected from the group consisting of CVD TaN, TiN, W and CVD Al.
14. A method as defined by claim 13 , wherein said material for said upper metal lines comprises CVD TiN, and said material for said contact plugs comprises W.
15. A method as defined by claim 10 , wherein said material for said contact plugs is selected from the group consisting of CVD TaN, TiN, W and CVD Al.
16. A method as defined by claim 15 , wherein said material for said contact plugs comprises W.
17. A method as defined by claim 10 , wherein forming the insulation layer comprises depositing the insulation layer, then planarizing the insulation layer by a chemical mechanical polishing (“CMP”) process.
18. A method as defined by claim 10 , wherein planarizing the material for the upper metal lines comprises a chemical mechanical polishing (“CMP”) process.