Semiconductor devices and methods for fabricating the same
View Patent ↗Semiconductor devices having a dual gate and method for fabricating the same are disclosed. A disclosed example method comprises: forming dummy gates in a semiconductor substrate; sequentially forming a lightly doped drain (LDD) region, a spacer and a source/drain; depositing an insulation film above the semiconductor substrate; exposing the dummy gates by planarizing the insulation film; removing the dummy gates; selectively injecting impurities into a region associated with at least one of the removed dummy gates; forming gate oxide films having different thicknesses on the regions associated with the removed dummy gates; depositing a polysilicon layer above the gate oxide films; and then forming polysilicon gates by planarizing the polysilicon layer.
1. A method for fabricating a semiconductor device, comprising:
forming first and second dummy gates in a semiconductor substrate;
forming a lightly doped drain (LDD), a spacer and a source/drain;
depositing an insulation film above the semiconductor substrate;
exposing the first and second dummy gates by planarizing the insulation film;
removing the first and second dummy gates;
selectively injecting impurities into a region associated with the first dummy gate;
forming a first gate oxide film having a first thickness in the region associated with the first dummy gate and forming a second gate oxide film having a second thickness in a region associated with the second dummy gate, the first thickness being different than the second thickness;
depositing a polysilicon layer above the first and second gate oxide films; and
forming first and second polysilicon gates by planarizing the polysilicon layer.
2. A method as defined in claim 1 , wherein forming the first and second dummy gates further comprises depositing a film formed of inorganic material such as silicon nitride (SiN) and patterning the deposited film.
3. A method as defined in claim 2 , wherein patterning the deposited film comprises exposure and development processes using a photoresist.
4. A method as defined in claim 2 , wherein a wet etching process using hot phosphoric acid is used in removing the first and second dummy gates.
5. A method as defined in claim 2 , wherein the impurities comprise one selected from a group consisting of As, P and Sb.
6. A method as defined in claim 2 , wherein at least one of a chemical mechanical polishing (CMP) method and an etch back method is used to planarize at least one of the insulation film and the polysilicon layer.
7. A method as defined in claim 1 , wherein forming the first and second dummy gates further comprises depositing a film formed of organic material and patterning the deposited film.
8. A method as defined in claim 7 , wherein the deposited film comprises polyimide.
9. A method as defined in claim 7 , wherein patterning the deposited film comprises exposure and development processes using a photoresist.
10. A method as defined in claim 7 , wherein removing the first and second dummy gates comprises an oxygen (O 2 ) plasma ashing process.
11. A method as defined in claim 7 , wherein the impurities comprises one selected from a group consisting of As, P and Sb.
12. A method as defined in claim 7 , wherein at least one of a chemical mechanical polishing (CMP) method and an etch back method is used to planarize at least one of the insulation film and the polysilicon.