IP Library Granted Patent US 6,960,520
Granted Patent B2
US 6,960,520 · App. 10/749,485 · Granted Nov 1, 2005

Method for forming metal lines in a semiconductor device

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Quick Facts
Patent No.
US 6,960,520
App. No.
10/749,485
Granted
Nov 1, 2005
Kind
B2
Abstract

A method for forming metal lines in a semiconductor device is disclosed. An example method forms first metal lines and a first insulation layer on the first metal lines, etches the first insulation layer to expose the first metal lines, and deposits a conductive material into the etched portion of the first insulation layer to form contact plugs. The example method also forms a second insulation layer on the resultant structure, etches the second insulation layer to expose the contact plugs, deposits a material for cores into the etched portions of the second insulation layer to form the cores, and selectively removes the second insulation layer to expose the cores. In addition, the example method deposits second metal lines on both sides of the cores to branch current to both sides of the cores.

Claims (12)

1. A method for forming metal lines in a semiconductor device, comprising:

forming first metal lines and a first insulation layer on the first metal lines;

etching the first insulation layer to expose the first metal lines;

depositing a conductive material into the etched portion of the first insulation layer to form contact plugs;

forming a second insulation layer on the first insulation layer and the contact plugs

etching the second insulation layer to expose the contact plugs;

depositing a material for cores into the etched portions of the second insulation layer to form the cores;

selectively removing the second insulation layer to expose the cores; and

depositing second metal lines on both sides of the cores to branch current to both sides of the cores.

2. The method of claim 1 , wherein the material for the cores is TaN or TiN.

3. The method of claim 1 , wherein in forming the second insulation layer, a nitride layer is formed on the first insulation layer and the contact plugs prior to the formation of the second insulation layer, and in etching the second insulation layer, the second insulation layer and the nitride layer are sequentially etched to expose the contact plugs.

4. The method of claim 3 , wherein the nitride layer is used for etch-stop.

Assignments (4)
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNOR PREVIOUSLY RECORDED ON REEL 017703 FRAME 0499. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNOR SHOULD BE "DONGBUANAM SEMICONDUCTOR INC.". Recorded Jun 28, 2006
From: DONGBUANAM SEMICONDUCTOR INC.
To: DONGBU ELECTRONICS CO., LTD.
Reel/Frame 017854/0297 →
CHANGE OF NAME Recorded May 30, 2006
From: DONGANAM SEMICONDUCTOR INC.
To: DONGBU ELECTRONICS CO., LTD.
Reel/Frame 017703/0499 →
MERGER Recorded May 31, 2005
From: DONGBU SEMICONDUCTOR INC.
To: DONGBUANAM SEMICONDUCTOR, INC.
Reel/Frame 016593/0667 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 26, 2004
From: PARK, CHEOLSOO
To: DONGBU ELECTRONICS CO., LTD.
Reel/Frame 014915/0593 →