Multiple power mode amplifier with bias modulation option and without bypass switches
View Patent ↗A multiple power mode amplifier provides a low and a high power mode without using switches. This amplifier may be used in radio frequency (RF) applications such as mobile telephones, pagers, portable digital assistants, and wireless e-mail devices. In the low power mode, the power consumption of the amplifier is reduced, which will increase operation time, especially important for battery-operated devices. In one implementation, the amplifier includes a number of impedance matching network units ( 130, 140, 150 , and 160 ), impedance transformer ( 170 ), and a power stage ( 120 ). An implementation provides further power consumption savings by modulating a bias of an amplifier stage.
1. An integrated circuit comprising:
a first transistor coupled between an input node and a first node;
a first impedance matching circuit coupled between the first node and a second node;
a second impedance matching circuit coupled between the second node and a third node;
a second transistor coupled between the third node and a fourth node;
a third impedance matching circuit coupled between the fourth node and a fifth node; and
an impedance transforming circuit coupled between the second node and the fifth node,
wherein in a first mode of operation, a signal provided at the input node passes through the first transistor, first impedance matching circuit, and impedance transforming circuit, and
in a second mode of operation, the signal provided at the input node passes through the first transistor, first impedance matching circuit, second impedance matching circuit, second transistor, and third impedance matching circuit.
2. The integrated circuit of claim 1 , wherein the impedance transforming circuit comprises:
an inductance device coupled between the second node and a sixth node; and
a capacitor coupled between the sixth node and fifth node, wherein the inductance device comprises at least one of an inductor, wire bonding, transmission line, microstrip line, strip line, coaxial cable, or coplanar waveguide.
3. The integrated circuit of claim 1 , wherein the impedance transforming circuit comprises:
a capacitor coupled between the second node and a sixth node; and
an inductance device coupled between the sixth node and the fifth node, wherein the inductance device comprises at least one of an inductor, wire bonding, transmission line, microstrip line, strip line, coaxial cable, or coplanar waveguide.
4. The integrated circuit of claim 1 , wherein the impedance transforming circuit comprises:
a first capacitor coupled between the second node and a sixth node;
an inductance device coupled between the sixth node and the fifth node; and
a second capacitor coupled between the sixth node and a reference voltage level, wherein the inductance device comprises at least one of an inductor, wire bonding, transmission line, microstrip line, strip line, coaxial cable, or coplanar waveguide.
5. The integrated circuit of claim 1 , wherein the impedance transforming circuit comprises:
an inductance device coupled between the second node and a sixth node;
a first capacitor coupled between the sixth node and the fifth node; and
a second capacitor coupled between the sixth node and a reference voltage level, wherein the inductance device comprises at least one of an inductor, wire bonding, transmission line, microstrip line, strip line, coaxial cable, or coplanar waveguide.
6. The integrated circuit of claim 1 , wherein the impedance transforming circuit comprises:
an inductance device coupled between the second node and the fifth node; and
a capacitor coupled between the second node and the fifth node, wherein the inductance device comprises at least one of an inductor, wire bonding, transmission line, microstrip line, strip line, coaxial cable, or coplanar waveguide.
7. The integrated circuit of claim 1 , wherein the impedance transforming circuit comprises:
an inductance device coupled between the second node and the fifth node;
a first capacitor coupled between the second node and a reference voltage level; and
a second capacitor coupled between the fifth node and the reference voltage level, wherein the inductance device comprises at least one of an inductor, wire bonding, transmission line, microstrip line, strip line, coaxial cable, or coplanar waveguide.
8. The integrated circuit of claim 1 , wherein the impedance transforming circuit comprises:
an inductance device, coupled between the second node and the fifth node, wherein the inductance device comprises at least one of an inductor, wire bonding, transmission line, microstrip line, strip line, coaxial cable, or coplanar waveguide.
9. The integrated circuit of claim 1 , wherein the third impedance matching circuit comprises:
an inductance device coupled between the fourth node and the fifth node; and
a capacitor coupled between the fourth node and a reference voltage level, wherein the inductance device comprises at least one of an inductor, wire bonding, transmission line, microstrip line, strip line, coaxial cable, or coplanar waveguide.
10. The integrated circuit of claim 1 , wherein the third impedance matching circuit comprises:
a first capacitor coupled between the fourth node and a reference voltage level;
a first inductance device coupled between the fourth node and the reference voltage level; and
a second inductance device coupled between the fourth node and the fifth node, wherein the first inductance device comprises at least one of an inductor, wire bonding, transmission line, microstrip line, strip line, coaxial cable, or coplanar waveguide, and the second inductance device comprises at least one of an inductor, wire bonding, transmission line, microstrip line, strip line, coaxial cable, or coplanar waveguide.
11. The integrated circuit of claim 1 , wherein the third impedance matching circuit comprises:
a first inductance device coupled between the fourth node and a reference voltage level;
a first capacitor coupled between the fourth node and the reference voltage level;
a second inductance device coupled between the fourth node and the fifth node; and
a second capacitor coupled between the fifth node and the reference voltage level, wherein the first inductance device comprises at least one of an inductor, wire bonding, transmission line, microstrip line, strip line, coaxial cable, or coplanar waveguide, and the second inductance device comprises at least one of an inductor, wire bonding, transmission line, microstrip line, strip line, coaxial cable, or coplanar waveguide.
12. The integrated circuit of claim 1 , wherein the third impedance matching circuit comprises:
a first inductance device coupled between the fourth node and a reference voltage level;
a second inductance device coupled between the fourth node and the fifth node; and
a first capacitor coupled between the fifth node and the reference voltage level, wherein the first inductance device comprises at least one of an inductor, wire bonding, transmission line, microstrip line, strip line, coaxial cable, or coplanar waveguide, and the second inductance device comprises at least one of an inductor, wire bonding, transmission line, microstrip line, strip line, coaxial cable, or coplanar waveguide.
13. The integrated circuit of claim 1 , wherein the third impedance matching circuit comprises:
a first capacitor coupled between the fourth node and a reference voltage level;
a first inductance device coupled between the fourth node and the fifth node; and
a second inductance device coupled between the fifth node and the reference voltage level, wherein the first inductance device comprises at least one of an inductor, wire bonding, transmission line, microstrip line, strip line, coaxial cable, or coplanar waveguide, and the second inductance device comprises at least one of an inductor, wire bonding, transmission line, microstrip line, strip line, coaxial cable, or coplanar waveguide.
14. The integrated circuit of claim 1 , wherein the first impedance matching circuit comprises a first capacitor coupled between the first node and a second node, and wherein the second circuit comprises a second capacitor coupled between the second node and a third node.
15. The integrated circuit of claim 1 , wherein the first impedance matching circuit comprises no passive elements coupled between the first node and a second node, and the second impedance matching circuit comprises a second capacitor coupled between the second node and a third node.
16. The integrated circuit of claim 14 , wherein the first impedance matching circuit further comprises an inductance device and a third capacitor, in series, coupled between the first node and a reference voltage level, wherein the inductance device comprises at least one of an inductor, wire bonding, transmission line, microstrip line, strip line, coaxial cable, or coplanar waveguide.
17. The integrated circuit of claim 16 , wherein the inductance device is further coupled to a supply voltage level.
18. The integrated circuit of claim 14 , wherein the second circuit further comprises an inductance device coupled between the second node and a reference voltage level, wherein the inductance device comprises at least one of an inductor, wire bonding, transmission line, microstrip line, strip line, coaxial cable, or coplanar waveguide.
19. The integrated circuit of claim 16 , wherein the second impedance matching circuit further comprises an inductance device coupled between the second node and the reference voltage level.
20. The integrated circuit of claim 14 , wherein the second impedance matching circuit further comprises an inductance device coupled between the third node and a reference voltage level, wherein the inductance device comprises at least one of an inductor, wire bonding, transmission line, micros trip line, strip line, coaxial cable, or coplanar waveguide.
21. The integrated circuit of claim 14 , wherein the second impedance matching circuit further comprises a third capacitor coupled between the second node and a reference voltage level.
22. The integrated circuit of claim 1 , wherein the first impedance matching circuit comprises an inductance device coupled between the first node and a reference voltage level, wherein the inductance device comprises at least one of an inductor, wire bonding, transmission line, microstrip line, strip line, coaxial cable, or coplanar waveguide.
23. The integrated circuit of claim 1 , wherein the second impedance matching circuit comprises:
a first capacitor coupled between the second node and a sixth node;
an inductance device coupled between the sixth node and a reference voltage level; and
a second capacitor coupled between the sixth node and the third node, wherein the inductance device comprises at least one of an inductor, wire bonding, transmission line, microstrip line, strip line, coaxial cable, or coplanar waveguide.
24. The integrated circuit of claim 1 , further comprising
a voltage control circuit coupled to the second transistor, wherein the voltage control circuit, in response to a mode control voltage, provides a control signal to the second transistor to place the second transistor in an on state or an off state.
25. The integrated circuit of claim 24 , wherein the voltage control circuit comprises a third transistor coupled between the second transistor and a reference voltage level, wherein an electrode of the third transistor is coupled to a voltage control line.
26. The integrated circuit of claim 24 , wherein the voltage control circuit comprises a third transistor coupled between the second transistor and a reference voltage level and a fourth transistor coupled between a supply voltage line and a reference voltage level, wherein an electrode of the third transistor is connected to the coupled point of the fourth transistor toward the supply voltage line and an electrode of the fourth transistor is coupled to a voltage control line.
27. The integrated circuit of claim 24 , wherein the voltage control circuit comprises a third transistor coupled between the second transistor and a reference voltage level and a fourth transistor coupled between a supply voltage line and an electrode of the third transistor, wherein an electrode of the third transistor is coupled to the fourth transistor and an electrode of the fourth transistor is coupled to a voltage control line.
28. The integrated circuit of claim 1 , wherein the first transistor or the second transistor is a bipolar junction transistor, a heterojunction bipolar transistor, a field effect transistor, a complementary metal-oxide semiconductor transistor, a metal-oxide semiconductor transistor, p-type metal-oxide semiconductor transistor, n-type metal-oxide semiconductor transistor, a high electron mobility transistor, or a metal semiconductor field effect transistor.
29. An amplifier circuit comprising:
an input node configured to couple a signal transmitted through a first set of impedance matching networks coupled in series between the input node and a second node;
a second set of impedance matching network and a power amplification stage coupled in series between the second node and a third node, wherein at least one of the second set of impedance matching networks provides a low impedance signal path to the signal in a first operational state of the amplifier circuit and a high impedance path to the signal in a second operational state of the amplifier circuit; and
a set of impedance transforming networks coupled in parallel to the second set of impedance matching networks and the power amplification stage, wherein the set of impedance transforming networks in cooperation with the first set of impedance matching networks provides a low impedance path to the signal when the second set of impedance matching networks in cooperation with the first set of impedance matching networks and power amplification stage provides a high impedance path to the signal.
30. The amplifier circuit of claim 29 , wherein the first set of impedance matching networks comprises at least one impedance matching network.
31. The amplifier circuit of claim 29 , wherein the second set of impedance matching networks comprises at least one impedance matching network.
32. The amplifier circuit of claim 29 , wherein the power amplification stage is responsive to a voltage control signal, wherein when the voltage control signal is at a first level, the power amplification stage is set to attenuate the signal, and when the voltage control signal is at a second level, the power amplification stage is set to amplify the signal.
33. The amplifier circuit of claim 29 , wherein when in the first operational state, the signal path defined by the first set of impedance matching networks, the second set of impedance matching networks, and the power amplification stage provides a low impedance path for the signal between the input node and the third node.
34. The amplifier circuit of claim 29 , wherein when in the first operational state, the signal path defined by the first set of impedance matching networks and the set of impedance transforming networks provides a high impedance path for the signal between the input node and the third node.
35. The amplifier circuit of claim 29 , wherein when in the second operational state, the signal path defined by the first set of impedance matching networks, the second set of impedance matching networks, and the power amplification stage provides a high impedance path for the signal between the input node and the third node.
36. The amplifier circuit of claim 29 , wherein when in the second operational state, the signal path defined by the first set of impedance matching networks and the set of impedance transforming networks provides a low impedance path for the signal between the input node and the third node.
37. A method of amplifying a signal, the method comprising:
transmitting a signal along a first signal path defined by a first set of impedance matching networks and a power amplification stage, wherein the first signal path is disposed between an input node and an output node;
transmitting the signal along a second signal path defined by the first set of impedance matching networks and a set of impedance transforming networks coupled in series between the input node and the output node, wherein the set of impedance transforming networks define a segment of the second signal path disposed in parallel with the first signal path; and
configuring the first signal path and the second signal path to different impedance states with respect to a mode of signal amplification.
38. The method of claim 37 , further comprising configuring the first signal path to a low impedance state and the second signal path to high impedance state when in a first power mode.
39. The method of claim 38 , further comprising configuring the power amplification stage to amplify the signal when in the first power mode state.
40. The method of claim 38 , further comprising configuring the power amplification stage to attenuate the signal when in a second power mode.
41. The method of claim 37 , further comprising transmitting the signal from the input node to an input of the second set of impedance matching networks and an input of the set of impedance transforming networks.
42. The method of claim 41 , wherein when in a first power mode a majority of the signal is transmitted along the second signal path and reflected from the first signal path.
43. The method of claim 41 , wherein when in the second power mode a majority of the signal is transmitted along the first signal path and reflected from the second signal path.