IP Library Granted Patent US 7,197,681
Granted Patent B2
US 7,197,681 · App. 10/750,949 · Granted Mar 27, 2007

Accelerated scan circuitry and method for reducing scan test data volume and execution time

Assignee: On-Chip Technologies, Inc.
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Quick Facts
Patent No.
US 7,197,681
App. No.
10/750,949
Granted
Mar 27, 2007
Kind
B2
Abstract

An architecture and methodology for test data compression using combinational functions to provide serial coupling between consecutive segments of a scan-chain are described. Compressed serial-scan sequences are derived starting from scan state identifying desired Care_In values and using symbolic computations iteratively in order to determine the necessary previous scan-chain state until computed previous scan-chain state matches given known starting scan-chain state. A novel design for a new flip-flop is also presented that allows implementing scan-chains that can be easily started and stopped without requiring an additional control signal. Extensions of the architecture and methodology are discussed to handle unknown (X) values in scan-chains, proper clocking of compressed data into multiple scan-chains, the use of a data-spreading network and the use of a pseudo-random signal generator to feed the segmented scan-chains in order to implement Built In Self Test (BIST).

Claims (24)

1. A method for computing compressed serial scan-in values for a scan-chain, said method comprising:

beginning with a desired scan-chain state as an initial current scan-chain state, said desired scan-chain state comprising one or more care-in values and zero or more don't-care values, repeatedly computing a previous scan-chain state and serial scan-in input value that must have existed one shift cycle prior to said current scan-chain state and setting said previous scan-chain state as the said current scan-chain state, until said current scan-chain state has pre-determined values in pre-determined bit positions of said scan-chain; and

forming said compressed serial scan-in values from said computed serial scan-in input values.

2. A method as described in claim 1 , wherein said compressed serial scan-in input values are generated using a data spreading network that receives a multiplicity of external serial input values that are used to generate a greater number of said serial scan-in input values than said multiplicity of external serial input values.

3. A method as described in claim 1 , where said scan-chain comprises a multiplicity of scan-chain segments, wherein inserting serial data into said scan-chain segments is performed by combining a next bit value of said serial scan-in input and a multiplicity of present values of scan-chain bit positions previous to the first bit positions of said scan-chain segments.

4. A method as described in claim 3 , wherein said compressed serial scan-in input values are generated using a data spreading network that receives a multiplicity of external serial input values that are used to generate a greater number of said serial scan-in input values than said multiplicity of external serial input values.

5. A method of testing an integrated circuit comprising at least one scan-chain, at least one said scan-chain comprising a multiplicity of scan-chain segments, said method comprising:

loading at least one of said at least one scan chain using compressed serial scan-in values determined according to the method of claim 4 .

6. A method as described in claim 1 , wherein said forming comprises:

taking said computed serial scan-in input values in reverse order.

7. A method of testing an integrated circuit that contains scan-chains using compressed scan-chain patterns, wherein at least one of said compressed scan-chain patterns is computed according to the method of claim 1 .

8. A machine-readable medium that provides instructions that, when executed by a computing platform, cause said computing platform to perform operations comprising the method according to claim 1 .

9. A method to compute compressed sequences of values for decompression by a data spreading network,said method comprising:

starting with sequences of don't care and care-in values desired to be produced by said data-spreading network, applying successive values from said sequences of don't care and care-in values to the outputs of said data spreading network;

resolving values on the inputs of said data spreading network associated with said outputs of said data spreading network, to produce resolved values; and

forming said compressed sequences of values as compressed sequences from said resolved values.

10. A method as in claim 9 , wherein said resolving values on the inputs of said data spreading network comprises:

generating one or more symbolic expressions associated with said inputs, said one or more symbolic expressions being formed as functions of input variables and said successive values applied to the outputs of said data spreading network; and

resolving values of said input variables and said one or more symbolic expressions.

11. A method as in claim 9 , wherein said resolving values on the inputs of said data spreading network comprises:

generating one or more symbolic expressions associated with said inputs and a set of one or more state variables that represent an internal state of said data spreading network, said one or more symbolic expressions being formed as functions of one or more of the following: input variables; said successive values applied to the outputs of said data spreading network; and present values of said one or more state variables;

replacing present values of said one or more state variables with symbolic expressions associated with said one or more state variables; and

resolving values of said input variables and said symbolic expressions.

12. A machine-readable medium that provides instructions that, when executed by a computing platform, cause said computing platform to perform operations comprising the method according to claim 9 .

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 19, 2018
From: INTELLECTUAL VENTURES ASSETS 81 LLC
To: AMERICAN PATENTS LLC
Reel/Frame 046405/0078 →
MERGER Recorded Dec 7, 2010
From: OC APPLICATIONS RESEARCH LLC
To: INTELLECTUAL VENTURES I LLC
Reel/Frame 025467/0063 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 4, 2008
From: ON-CHIP TECHNOLOGIES, INC.
To: OC APPLICATIONS RESEARCH LLC
Reel/Frame 020753/0337 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 5, 2004
From: DERVISOGLU, BULENT; COOKE, LAURENCE H.
To: ON-CHIP TECHNOLOGIES, INC.
Reel/Frame 014872/0001 →
Continuity (3)
Continuation In Part 1035127600 · Jan 24, 2003
Provisional Application 6028768300 · Jun 11, 2002
Related Publication 20040148554A1 · Jul 29, 2004