Integrated ONO processing for semiconductor devices using in-situ steam generation (ISSG) process
A process for fabrication of a semiconductor device including an ONO structure as a component of a flash memory device, comprising forming the ONO structure by providing a semiconductor substrate having a silicon surface; forming a first oxide layer on the silicon surface; depositing a silicon nitride layer on the first oxide layer; and forming a top oxide layer on the silicon nitride layer, wherein the top oxide layer is formed by an in-situ steam generation oxidation of a surface of the silicon nitride layer. The semiconductor device may be, e.g., a SONOS two-bit EEPROM device or a floating gate FLASH memory device including an ONO structure.
1. A process for fabrication of a semiconductor device including an ONO structure as a component of a flash memory device, comprising forming the ONO structure by:
providing a semiconductor substrate having a silicon surface;
forming a first oxide layer on the silicon surface;
depositing a silicon nitride layer on the first oxide layer; and
forming a top oxide layer on the silicon nitride layer,
wherein the top oxide layer is formed by an in-situ steam generation oxidation of a surface of the silicon nitride layer at an absolute pressure in the range from about 50 to about 500 torr.
2. The process of claim 1 , wherein the flash memory device comprises a two-bit EEPROM device or a floating gate FLASH device.
3. The process of claim 2 , wherein the flash memory device is a two-bit EEPROM device in which the first oxide layer is a tunnel oxide layer, and the tunnel oxide layer is formed by an in-situ steam generation oxidation of the silicon surface.
4. The process of claim 2 , wherein the flash memory device is a floating gate FLASH device in which the first oxide layer is a bottom oxide layer, and the bottom oxide layer is formed by an in-situ steam generation oxidation of the silicon surface.
5. The process of claim 1 , wherein the steps of forming a first oxide layer, depositing a silicon nitride layer and forming a top oxide layer are carried out in an RTP and RTCVD apparatus or in a single-wafer cluster tool.
6. The process of claim 1 , wherein the step of forming a first oxide layer is carried out by an in-situ steam generation oxidation of the silicon surface.
7. The process of claim 1 , wherein each step of in-situ steam generation oxidation is carried out by providing a hydrogen-containing gas and an oxygen-containing gas to an RTP system or to a single-wafer cluster tool.
8. The process of claim 1 , wherein the in-situ steam generation oxidation is carried out at a temperature in the range from about 850° C. to about 1150° C.
9. The process of claim 1 , wherein the step of depositing a silicon nitride layer comprises RTCVD using about 0.5 to 2 slpm ammonia and about 20 to about 50 sccm of a second gas selected from the group consisting of silane and dichlorosilane.
10. The process of claim 9 , wherein the RTCVD process comprises a three step sequence including a temperature ramp up step, a deposition step of about 2 minutes, and a cool down step.
11. The process of claim 1 , wherein the silicon nitride layer is deposited to a thickness of about 50 to about 300 angstroms.
12. The process of claim 1 , wherein the top oxide layer is formed to a thickness of about 50 to about 150 angstroms.
13. A process for fabrication of a semiconductor device, the device including a two-bit EEPROM device including an ONO structure, comprising forming the ONO structure by:
providing a semiconductor substrate having a silicon surface;
forming a tunnel oxide layer overlying the silicon surface;
depositing a silicon nitride layer overlying the tunnel oxide layer; and
forming a top oxide layer overlying the silicon nitride layer by in-situ steam generation oxidation of a portion of the silicon nitride layer at an absolute pressure in the range from about 50 to about 500 torr.
14. The process of claim 13 , wherein the steps of forming a tunnel oxide layer, depositing a silicon nitride layer and forming a top oxide layer are carried out in an RTP apparatus which is a component of a single-wafer cluster tool.
15. The process of claim 12 , wherein the step of in-situ steam generation oxidation is carried out at a temperature in the range from about 850° C. to about 1150° C. and by providing hydrogen gas and oxygen gas to the RTP apparatus.
16. The process of claim 13 , wherein the step of forming a tunnel oxide layer is carried out by an in-situ steam generation oxidation of the silicon surface.
17. A process for fabrication of a semiconductor device, the device including a floating gate FLASH memory device comprising an ONO structure, comprising forming the ONO structure by:
providing a semiconductor substrate having a floating gate electrode;
forming a bottom oxide layer overlying the floating gate electrode;
depositing a silicon nitride layer overlying the tunnel oxide layer; and
forming a top oxide layer overlying the silicon nitride layer by in-situ steam generation oxidation of a portion of the silicon nitride layer at an absolute pressure in the range from about 50 to about 500 torr.
18. The process of claim 17 , wherein the steps of forming a bottom oxide layer, depositng a silicon nitride layer and forming a top oxide layer are carried out in an RTP apparatus which is a component of a single-wafer cluster tool.
19. The process of claim 17 , wherein each step of in-situ steam generation oxidation is carried out at a temperature in the range from about 850° C. to about 1150° C. and by providing hydrogen gas and oxygen gas to the RTP apparatus.
20. The process of claim 17 , wherein the step of forming a bottom oxide layer is carried out by an in-situ steam generation oxidation of a portion of the floating gate electrode.