Low stress sidewall spacer in integrated circuit technology
View Patent ↗A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. Source/drain junctions are formed in the semiconductor substrate. A sidewall spacer is formed around the gate using a low power plasma enhanced chemical vapor deposition process A silicide is formed on the source/drain junctions and on the gate, and an interlayer dielectric is deposited above the semiconductor substrate. Contacts are then formed in the interlayer dielectric to the silicide.
1. A method of forming an integrated circuit comprising:
providing a semiconductor substrate;
forming a gate dielectric on the semiconductor substrate;
forming a gate on the gate dielectric;
forming source/drain junctions in the semiconductor substrate;
forming a sidewall spacer around the gate using a low bias power plasma enhanced chemical vapor deposition process;
forming a silicide on the source/drain junctions and on the gate at an extra slow rate of deposition of silicide metal;
depositing an interlayer dielectric above the semiconductor substrate; and
forming contacts in the interlayer dielectric to the silicide.
2. The method as claimed in claim 1 wherein:
forming the sidewall spacer uses a low bias power plasma enhanced chemical vapor deposition process in the range of about 100 watts to about 200 watts.
3. The method as claimed in claim 1 wherein:
forming the silicide uses an ultra-thin thickness of a silicide metal.
4. The method as claimed in claim 1 wherein:
depositing the interlayer dielectric deposits a dielectric material having a dielectric constant of at least one of medium, low, or ultra-low dielectric constants.
5. The method as claimed in claim 1 wherein:
forming the contacts to the silicide uses at least one of tantalum, titanium, tungsten, copper, gold, silver, an alloy thereof, a compound thereof, or a combination thereof.
6. The method as claimed in claim 1 wherein:
forming the silicide forms a nickel silicide.
7. The method as claimed in claim 1 wherein:
forming the silicide forms a nickel silicide doped with arsenic.
8. The method as claimed in claim 1 wherein:
forming the silicide uses a low bias power deposition technique.
9. The method as claimed in claim 1 wherein:
forming the silicide forms a silicide of at least one of cobalt, titanium, nickel, an alloy thereof, a compound thereof, or a combination thereof.
10. The method as claimed in claim 1 wherein:
forming the sidewall spacer forms an insulating material of at least one of a nitride, an oxide, a compound thereof, or a combination thereof.
11. A method of reducing piping of a silicide under a sidewall spacer in an integrated circuit comprising:
forming the silicide using an extra slow rate of deposition of a silicide metal; and
forming the sidewall spacer using a low bias power plasma enhanced chemical vapor deposition process in the range of about 100 watts to about 200 watts.
12. The method as claimed in claim 11 wherein:
forming the silicide uses an ultra-thin thickness of a silicide metal.
13. The method as claimed in claim 11 wherein:
the silicide comprises a nickel silicide.
14. The method as claimed in claim 11 wherein:
the silicide comprises a nickel silicide doped with arsenic.
15. The method as claimed in claim 11 wherein:
the silicide comprises a silicide of at least one of cobalt, titanium, nickel, an alloy thereof, a compound thereof, or a combination thereof.