Patent Assignment
Reel/Frame 075498/0156
Assignment of Assignor's Interest
Recorded: 2026-04-08
Received: 2026-08-03
Pages: 10
Assignor
INNOVATIVE FOUNDRY TECHNOLOGIES LLC
Executed: 2025-09-04
Assignee
SEMIFAB IP INNOVATIONS, LLC
4802 PARKVIEW PLACE, AUSTIN, TX, 78731, UNITED STATES
Covered Properties
(59)
Integrated Circuit with Metal and Semi-Conducting Gate
Application:
13/644,387 →
Method of Forming Finned Semiconductor Devices with Trench Isolation
Application:
13/176,614 →
Transistor Having a Channel with Tensile Strain and Oriented Along a Crystallographic Orientation with Increased Charge Carrier Mobility
Application:
12/821,308 →
Stress Enhanced Transistor
Application:
12/644,882 →
Contact Trenches for Enhancing Stress Transfer in Closely Spaced Transistors
Application:
12/469,972 →
Semiconductor Devices Having Faceted Silicide Contacts, and Related Fabrication Methods
Application:
12/249,570 →
Cmos Circuit Having a Tensile Stress Layer Overlying an Nmos Transistor and Overlapping a Portion of a Compressive Stress Layer.
Application:
12/199,659 →
Semiconductor Circuit Including a Long Channel Device and a Short Channel Device
Application:
12/181,180 →
Method of Forming Finned Semiconductor Devices with Trench Isolation
Application:
12/176,866 →
Hybrid Contact Structure with Low Aspect Ratio Contacts in a Semiconductor Device
Application:
12/131,332 →
Semiconductor Chip with Stratified Underfill
Application:
11/849,545 →
Integrated Circuit System with Metal and Semi-Conducting Gate
Application:
11/611,856 →
Stress Enhanced Transistor and Methods for Its Fabrication
Application:
11/611,784 →
Transistor Having a Channel with Tensile Strain and Oriented Along a Crystallographic Orientation with Increased Charge Carrier Mobility
Application:
11/567,268 →
Stress Enhanced Mos Transistor and Methods for Its Fabrication
Application:
11/562,209 →
Method for Forming Embedded Strained Drain/Source Regions Based on a Combined Spacer and Cavity Etch Process
Application:
11/559,462 →
Method of Increasing the Etch Selectivity in a Contact Structure of Semiconductor Devices
Application:
11/538,111 →
Fabrication Methods for Stress Enhanced Cmos Circuits
Application:
11/532,753 →
Formation of Abrupt Junctions in Devices by Using Silicide Growth Dopant Snowplow Effect
Application:
11/422,811 →
Composite Barrier Layers with Controlled Copper Interface Surface Roughness
Application:
11/376,190 →
Technique for Forming a Contact Insulation Layer with Enhanced Stress Transfer Efficiency
Application:
11/288,673 →
System and Method for Improving Reliability in a Semiconductor Device
Application:
11/186,969 →
Decoupling Capacitor Density While Maintaining Control Over Aclv Regions on a Semiconductor Integrated Circuit
Application:
11/174,713 →
Technique for Creating Different Mechanical Strain in Different Channel Regions by Forming an Etch Stop Layer Stack Having Differently Modified Intrinsic Stress
Application:
11/150,635 →
Integrated Circuit and Method of Manufacture
Application:
11/119,660 →
Semiconductor Device Having a Retrograde Dopant Profile in a Channel Region
Application:
11/072,142 →
Composite Tantalum Nitride/Tantalum Copper Capping Layer
Application:
10/934,511 →
Semiconductor Component and Method of Manufacture
Application:
10/915,638 →
Method for Forming a Field Effect Transistor Having a High-K Gate Dielectric
Application:
10/899,955 →
In-Situ Nitride/Oxynitride Processing with Reduced Deposition Surface Pattern Sensitivity
Application:
10/887,836 →
Low Power Pre-Silicide Process in Integrated Circuit Technology
Application:
10/859,286 →
Strained Channel Finfet
Application:
10/833,112 →
Method of Forming Composite Barrier Layers with Controlled Copper Interface Surface Roughness
Application:
10/811,866 →
Low Stress Sidewall Spacer in Integrated Circuit Technology
Application:
10/756,023 →
Formation of Abrupt Junctions in Devices by Using Silicide Growth Dopant Snowplow Effect
Application:
10/727,999 →
Conformal Barrier Liner in an Integrated Circuit Interconnect
Application:
10/672,103 →
Method of Manufacturing an Integrated Circuit with Low Solubility Metal-Conductor Interconnect Cap
Application:
10/672,126 →
Method for Forming a Field Effect Transistor Having a High-K Gate Dielectric and Related Structure
Application:
10/618,273 →
Finfet Gate Formation Using Reverse Trim and Oxide Polish
Application:
10/459,589 →
Method for Forming Multiple Fins in a Semiconductor Device
Application:
10/429,780 →
Dual Damascene Integration Scheme for Preventing Copper Contamination of Dielectric Layer
Application:
10/422,784 →
Strained Channel Finfet
Application:
10/349,042 →
Method of Manufacturing a Semiconductor Component
Application:
10/284,651 →
Semiconductor Device Having a Retrograde Dopant Profile in a Channel Region and Method for Fabricating the Same
Application:
10/282,980 →
Method of Manufacturing a Semiconductor Component."
Application:
10/236,200 →
Method for Manufacturing a Scribe Seal Structure
Application:
10/177,336 →
Semiconductor Device and Fabrication Technique Using a High-K Liner for Spacer Etch Stop
Application:
10/163,930 →
Conformal Barrier Liner in an Integrated Circuit Interconnect
Application:
10/165,510 →
Semiconductor Packaging Appaats for Controlling Die Attach Fillet Height to Reduce Die Shear Stress
Application:
10/053,994 →
Integrated Circuit with Low Solubility Metal-Conductor Interconnect Cap
Application:
10/016,024 →
Integrated Circuit Interconnect Shunt Layer
Application:
09/905,479 →
Integration of Organic Fill for Dual Damascene Process
Application:
09/892,750 →
Mosfet with Sige Source/Drain Regions and Epitaxial Gate Dielectric
Application:
09/877,906 →
Self-Aligned Conductive Plugs in a Semiconductor Device
Application:
09/826,185 →
Method and Apparatus for Shielding Electromagnetic Emissions from an Integrated Circuit
Application:
09/824,148 →
Transistor Device Having an Enhanced Width Dimension and a Method of Making Same
Application:
09/812,521 →
Dual Damascene Integration Scheme for Preventing Copper Contamination of Dielectric Layer
Application:
09/793,993 →
Cu Damascene Interconnections Using Barrier/Capping Layer
Application:
09/783,619 →
Semiconductor Devices Utilizing Differently Composed Metal-Based in-Laid Gate Electrodes
Application:
09/781,436 →