Formation of abrupt junctions in devices by using silicide growth dopant snowplow effect
View Patent ↗A method of forming an abrupt junction device with a semiconductor substrate is provided. A gate dielectric is formed on a semiconductor substrate, and a gate is formed on the gate dielectric. A sidewall spacer is formed on the semiconductor substrate adjacent the gate and the gate dielectric. A thickening layer is formed by selective epitaxial growth on the semiconductor substrate adjacent the sidewall spacer. Raised source/drain dopant implanted regions are formed in at least a portion of the thickening layer. Silicide layers are formed in at least a portion of the raised source/drain dopant implanted regions to form source/drain regions, beneath the silicide layers, that are enriched with dopant from the silicide layers. A dielectric layer is deposited over the silicide layers, and contacts are then formed in the dielectric layer to the silicide layers.
1. A method of forming a device comprising:
providing a semiconductor substrate;
forming a gate dielectric on the semiconductor substrate;
forming a gate on the gate dielectric;
forming a sidewall spacer on the semiconductor substrate adjacent the gate and the gate dielectric;
forming a thickening layer by selective epitaxial growth on the semiconductor substrate adjacent the sidewall spacer;
forming raised source/drain dopant implanted regions in at least a portion of the thickening layer;
forming silicide layers in at least a portion of the raised source/drain dopant implanted regions to form source/drain regions, beneath the silicide layers, that are enriched with dopant from the silicide layers;
depositing a dielectric layer over the silicide layers; and
forming contacts in the dielectric layer to the silicide layers.
2. The method as claimed in claim 1 wherein forming the raised source/drain dopant implanted regions further comprises implanting dopant into the thickening layer and the adjacent top of the semiconductor substrate.
3. The method as claimed in claim 1 wherein forming silicide layers in the raised source/drain dopant implanted regions further comprises:
depositing metallic layers on the raised source/drain dopant implanted regions; and
forming silicide layers by thermal silicidation of the metallic layers into the material of the raised source/drain dopant implanted regions.
4. The method as claimed in claim 1 wherein forming silicide layers in the raised source/drain dopant implanted regions to form source/drain regions therebeneath that are enriched with dopant from the silicide layers further comprises forming source/drain regions that are enriched with a dopant profile that is steeper than the profile of the dopant as it was originally implanted.
5. The method as claimed in claim 1 wherein forming raised source/drain dopant implanted regions further comprises implanting the regions with a dopant selected from a group consisting of arsenic, phosphorus, antimony, boron, indium, and a combination thereof.
6. The method as claimed in claim 1 wherein forming silicide layers further comprises depositing a metallic layer selected from a group consisting of cobalt, nickel, titanium, hafnium, platinum, and a combination thereof.
7. A method of forming a device comprising:
providing a semiconductor substrate;
forming a gate dielectric on the semiconductor substrate;
forming a gate on the gate dielectric;
forming a sidewall spacer on the semiconductor substrate adjacent the gate and the gate dielectric;
forming a thickening layer by selective epitaxial growth of silicon on the surface of the semiconductor substrate adjacent the sidewall spacer and the gate;
forming raised source/drain dopant implanted regions in at least a portion of the thickening layer and the adjacent top of the semiconductor substrate;
forming silicide layers in at least a portion of the raised source/drain dopant implanted regions to form source/drain regions, beneath the silicide layers, that are enriched with dopant from the silicide layers;
forming a silicide layer on the gate;
depositing a dielectric layer over the silicide layers; and
forming contacts in the dielectric layer to the silicide layers.
8. The method as claimed in claim 7 wherein forming the raised source/drain dopant implanted regions further comprises implanting dopant into the thickening layer and the adjacent top of the semiconductor substrate.
9. The method as claimed in claim 7 wherein forming silicide layers in the raised source/drain dopant implanted regions further comprises:
depositing metallic layers on the raised source/drain dopant implanted regions; and
forming silicide layers by thermal silicidation of the metallic layers into the silicon material of the raised source/drain dopant implanted regions.
10. The method as claimed in claim 7 wherein forming silicide layers in the raised source/drain dopant implanted regions to form source/drain regions therebeneath that are enriched with dopant from the silicide layers further comprises forming source/drain regions that are enriched with a dopant profile that is steeper than the profile of the dopant as it was originally implanted.
11. The method as claimed in claim 7 wherein forming raised source/drain dopant implanted regions further comprises implanting the regions with a dopant selected from a group consisting of arsenic, phosphorus, antimony, boron, indium, and a combination thereof.
12. The method as claimed in claim 7 wherein forming silicide layers further comprises depositing a metallic layer selected from a group consisting of cobalt, nickel, titanium, hafnium, platinum, and a combination thereof.