Method of forming finned semiconductor devices with trench isolation

1. A method of manufacturing a semiconductor device structure, the method comprising:

providing a substrate comprising a bulk semiconductor material, a first conductive fin structure formed from the bulk semiconductor material, and a second conductive fin structure formed from the bulk semiconductor material, the first conductive fin structure and the second conductive fin structure being separated by a gap;

forming spacers in the gap and adjacent the first conductive fin structure and the second conductive fin structure, wherein the spacers are formed from an oxide material, and wherein forming the spacers fills in spaces between adjacent fins in each of the first and second conductive fin structures with the oxide material;

etching the bulk semiconductor material, using the spacers as an etch mask, to form an isolation trench in the bulk semiconductor material;

forming a dielectric material in the isolation trench, over the spacers, over the first conductive fin structure, over the second conductive fin structure, and over the oxide material in the spaces between adjacent fins in each of the first and second conductive fin structures; and

etching a portion of the dielectric material, a portion of the spacers, and a portion of the oxide material in the spaces between adjacent fins in each of the first and second conductive fin structures to expose an upper section of the first conductive fin structure and an upper section of the second conductive fin structure, while preserving the dielectric material in the isolation trench and preserving some of the oxide material in the spaces between and at the base of the adjacent fins in each conductive fin structure.

2. The method of claim 1 , wherein forming spacers comprises:

depositing the oxide material over the first conductive fin structure, the second conductive fin structure, and the bulk semiconductor material, the oxide material forming a recess that corresponds to the gap; and

anisotropically etching the oxide material such that the recess extends to the bulk semiconductor material.

3. The method of claim 1 , wherein etching the bulk semiconductor material forms the isolation trench such that it is self-aligned with the spacers.

4. The method of claim 1 , further comprising polishing the dielectric material to a height of the first conductive fin structure and the second conductive fin structure, prior to etching the portion of the dielectric material and the portion of the spacers.

5. The method of claim 4 , wherein the step of etching the portion of the dielectric material and the portion of the spacers uses an endpoint etching technique.

6. The method of claim 1 , further comprising:

completing fabrication of a first device structure that includes the first conductive fin structure; and

completing fabrication of a second device structure that includes the second conductive fin structure; wherein

the dielectric material in the isolation trench electrically isolates the first device structure from the second device structure.

7. A method of manufacturing a semiconductor device structure, the method comprising:

providing a substrate comprising a bulk semiconductor material, a first conductive fin structure formed from the bulk semiconductor material, and a second conductive fin structure formed from the bulk semiconductor material, the first conductive fin structure and the second conductive fin structure being separated by a gap;

forming spacers in the gap and adjacent the first conductive fin structure and the second conductive fin structure;

etching the bulk semiconductor material, using the spacers as an etch mask, to form an isolation trench in the bulk semiconductor material;

removing the spacers to expose conductive fins of the first and second conductive fin structures;

forming a dielectric material in the isolation trench, between adjacent conductive fins in the first conductive fin structure, between adjacent conductive fins in the second conductive fin structure, over the first conductive fin structure, and over the second conductive fin structure; and

etching a portion of the dielectric material to expose an upper section of the first conductive fin structure and an upper section of the second conductive fin structure, while preserving the dielectric material in the isolation trench, and retaining a layer of the dielectric material between and at the base of the adjacent fins in each conductive fin structure.

8. The method of claim 7 , wherein forming spacers comprises:

depositing an oxide material over the first conductive fin structure, the second conductive fin structure, and the bulk semiconductor material, the oxide material forming a recess that corresponds to the gap; and

anisotropically etching the oxide material such that the recess extends to the bulk semiconductor material.

9. The method of claim 7 , wherein etching the bulk semiconductor material forms the isolation trench such that it is self-aligned with the spacers.

10. The method of claim 7 , further comprising polishing the dielectric material to a height of the first conductive fin structure and the second conductive fin structure, prior to etching at least a portion of the dielectric material.

11. The method of claim 10 , wherein the step of etching at least a portion of the dielectric material uses an endpoint etching technique.

12. The method of claim 7 , further comprising:

completing fabrication of an NMOS transistor device structure that includes the first conductive fin structure; and

completing fabrication of a PMOS transistor device structure that includes the second conductive fin structure; wherein

the dielectric material in the isolation trench electrically isolates the NMOS transistor device structure from the PMOS transistor device structure.

13. The method of claim 7 , wherein removing the spacers comprises selectively etching away the spacers.