Low power pre-silicide process in integrated circuit technology
View Patent ↗A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. Source/drain junctions are formed in the semiconductor substrate. A thin insulating layer is formed over the source/drain junctions. A silicide is formed on the thin insulating layer and on the gate. An interlayer dielectric is deposited above the semiconductor substrate. Contacts are then formed in the interlayer dielectric to the silicide.
1. A method of forming an integrated circuit comprising:
providing a semiconductor substrate;
forming a gate dielectric on the semiconductor substrate;
forming a gate over the gate dielectric;
forming source/drain junctions in the semiconductor substrate;
forming a thin insulating layer having a thickness greater than zero and less than about 25 Angstroms over and in direct contact with the source/drain junctions;
forming a silicide on the thin insulating layer and on the gate;
depositing an interlayer dielectric above the semiconductor substrate; and
forming contacts in the interlayer dielectric to the silicide.
2. The method as claimed in claim 1 wherein:
forming the source/drain junctions comprises forming a liner layer over the source/drain junctions; and
forming the thin insulating layer uses a sputter process in the power range of about 200 to about 250 watts to remove a portion of the liner layer.
3. The method as claimed in claim 1 wherein:
forming the source/drain junctions comprises forming a liner layer over the source/drain junctions; and
forming the thin insulating layer uses an Argon sputter process in the power range of about 30 to about 35 watts to remove a portion of the liner layer.
4. The method as claimed in claim 1 wherein:
forming the silicide forms a silicide of a metal of at least one of cobalt, titanium nickel, an alloy thereof, a compound thereof, and a combination thereof.
5. A method of forming an integrated circuit comprising:
providing a semiconductor substrate;
forming a gate dielectric on the semiconductor substrate;
forming a gate over the gate dielectric;
forming a liner layer over the semiconductor substrate;
forming source/drain junctions in the semiconductor substrate through the liner layer;
forming a thin insulating layer over the source/drain junctions;
forming a silicide on the thin insulating layer and on the gate;
depositing an interlayer dielectric above the semiconductor substrate; and
forming contacts in the interlayer dielectric to the silicide.
6. The method as claimed in claim 5 wherein:
forming the thin insulating layer forms a layer having a thickness greater than zero and less than about 25 Angstrorms.
7. The method as claimed in claim 5 wherein:
forming the thin insulating layer uses a sputter process in the power range of about 200 to about 250 watts to remove a portion of the liner layer.
8. The method as claimed in claim 5 wherein:
forming the thin insulating layer uses an Argon sputter process in the power range of about 30 to about 35 watts to remove a portion of the liner layer.
9. The method as claimed in claim 5 wherein:
forming the silicide forms a silicide of a metal of at least one of cobalt, titanium, nickel, an alloy thereof, a compound thereof, and a combination thereof.
10. An integrated circuit comprising:
a semiconductor substrate;
a gate dielectric on the semiconductor substrate;
a gate over the gate dielectric;
source/drain junctions in the semiconductor substrate;
a thin insulating layer having a thickness greater than zero and less than about 25 Angstroms over and in direct contact with the source/drain junctions;
a silicide on the thin insulating layer and on the gate;
an interlayer dielectric above the semiconductor substrate; and
contacts in the interlayer dielectric to the silicide.
11. The integrated circuit as claimed in claim 10 wherein:
the contacts to the silicide comprise at least one of tantalum, titanium, tungsten, copper, gold, silver, an alloy thereof, a compound thereof, and a combination thereof.
12. The integrated circuit as claimed in claim 10 wherein:
the interlayer dielectric comprises a dielectric material having a dielectric constant of at least one of medium, low, or ultra-low dielectric constants.
13. The integrated circuit as claimed in claim 10 wherein:
the silicide comprises a silicide of a metal of at least one of cobalt, titanium, nickel, an alloy thereof, a compound thereof, and a combination thereof.
14. A method of reducing diffusion of a silicide in the area of a gate in an integrated circuit having source/drain junctions comprising:
forming a thin insulating layer having a thickness greater than zero and less than about 25 Angstroms over and in direct contact with the source/drain junctions; and
forming the silicide on the thin insulating layer and on the gate.
15. The method as claimed in claim 14 further comprising:
forming a liner layer over the source/drain junctions; and wherein
forming the thin insulating layer uses a sputter process in the power range of about 200 to about 250 watts to remove a portion of the liner layer.
16. The method as claimed in claim 14 further comprising:
forming a liner layer over the source/drain junctions; and wherein
forming the thin insulating layer uses an Argon sputter process in the power range of about 30 to about 35 watts to remove a portion of the liner layer.
17. The method as claimed in claim 14 wherein:
forming the silicide forms a silicide of a metal of at least one of cobalt, titanium, nickel, an alloy thereof, a compound thereof, and a combination thereof.