In-situ nitride/oxynitride processing with reduced deposition surface pattern sensitivity
View Patent ↗Carrier mobility in transistor channel regions is increased by depositing a conformal stressed liner. Embodiments include forming a silicon oxynitride layer on the stressed liner to reduce or eliminate deposition surface pattern sensitivity during gap filling, and in-situ SACVD of silicon oxide gap fill directly on the stressed liner with reduced pattern sensitivity. Embodiments also include the use of Si—Ge substrates.
1. A semiconductor device comprising:
a substrate;
a plurality of transistors formed on the substrate, each transistor comprising source/drain regions and a gate electrode, having an upper and side surfaces, over the substrate with a gate dielectric layer therebetween, the gate electrodes being separated by a gap;
a conformal stressed nitride liner over the upper and side surfaces of the gate electrodes and over the source/drain regions; and
a dielectric layer over the transistors and filling the gaps between the gate electrodes.
2. The semiconductor device according to claim 1 , further comprising a conformal silicon oxynitride layer on the stressed nitride liner, and the dielectric layer on the conformal silicon oxynitride layer filling the gaps.
3. The semiconductor device according to claim 1 , wherein the substrate comprises a layer of silicon (Si) having a strained lattice on a layer of silicon-germanium (Si—Ge).
4. The semiconductor device according to claim 3 , wherein:
the transistor is a P-channel transistor; and
the stressed nitride liner exhibits high compressive stress.
5. The semiconductor device according to claim 3 , wherein:
the transistor is an N-channel transistor; and
the stressed nitride liner exhibits high tensile stress.
6. The semiconductor device according to claim 1 , further comprising:
dielectric sidewall spacers on side surfaces of the gate electrodes; and
a layer of metal silicide on the upper surface of the gate electrodes and on the source/drain regions, wherein the stressed nitride liner is on the sidewall spacers and metal silicide layers.
7. The semiconductor device according to claim 6 , wherein:
the sidewall spacers comprise an oxide liner on the side surfaces of the gate electrode and on an upper surface portion of the substrate, and a nitride layer on the oxide liner.
8. The semiconductor device according to claim 1 , wherein:
the stressed nitride liner comprises silicon nitride and has a thickness of about 200 Å to about 1000 Å; and
the silicon oxynitride layer has a thickness of about 20 Å to about 40 Å.
9. The semiconductor device according to claim 8 , wherein the dielectric layer comprises silicon oxide and has a thickness of about 6,500 Å to about 7,500 Å.