Stress enhanced CMOS circuits and methods for their fabrication
View Patent ↗A stress enhanced CMOS circuit and methods for its fabrication are provided. One fabrication method comprises the steps of forming an NMOS transistor and a PMOS transistor adjacent the NMOS transistor in a channel width direction, the PMOS transistor and the NMOS transistor separated by an isolation region. A compressive stress liner is deposited overlying the transistors and the isolation region and is etched to remove the compressive stress liner from the NMOS transistor and from a portion of the isolation region. A tensile stress liner is deposited overlying the transistors, the isolation region, and the compressive stress liner and is etched to remove a portion of the tensile stress liner overlying a portion of the compressive stress liner and to leave the tensile stress liner overlying the NMOS transistor, the isolation region, and a portion of the compressive stress liner.
1. A method for fabricating a stress enhanced CMOS circuit comprising the steps of:
forming a first NMOS transistor and a second NMOS transistor;
forming a PMOS transistor adjacent the first NMOS transistor in a channel width direction and adjacent the second NMOS transistor in a channel length direction, the PMOS transistor and the first NMOS transistor separated by an isolation region therebetween;
depositing and patterning a dummy region positioned between the second NMOS transistor and the PMOS transistor;
depositing a compressive stress liner overlying the first NMOS transistor, the PMOS transistor, and the isolation region;
etching the compressive stress liner to remove the compressive stress liner from the first NMOS transistor and from a portion of the isolation region;
depositing a tensile stress liner overlying the first NMOS transistor, the PMOS transistor, and the isolation region; and
selectively etching the tensile stress liner to: remove a portion of the tensile stress liner overlying the compressive stress liner, and leave the tensile stress liner overlying the first NMOS transistor, the isolation region, a portion of the compressive stress liner and a portion of the PMOS transistor.
2. The method of claim 1 wherein the step of depositing a compressive stress liner comprises the step of depositing a first silicon nitride layer.
3. The method of claim 2 wherein the step of depositing a tensile stress liner comprises the step of depositing a second silicon nitride layer.
4. The method of claim 1 wherein the step of etching the compressive stress liner comprises the step of:
etching the compressive stress liner to leave a portion of the compressive stress liner overlying a portion of the dummy region and wherein the step of etching the tensile stress liner comprises the step of etching the tensile liner to leave a portion of the tensile stress liner overlying a portion of the dummy region and spaced apart from the portion of the compressive stress liner.
5. The method of claim 1 wherein the step of depositing and patterning a dummy region comprises the step of:
depositing and patterning a polycrystalline silicon dummy region.
6. A method for fabricating a stress enhanced CMOS circuit comprising the steps of:
forming a PMOS transistor;
forming a first NMOS transistor adjacent the PMOS transistor in a channel width direction and a second NMOS transistor adjacent the PMOS transistor in a channel length direction, the PMOS transistor separated from the first NMOS transistor and the second NMOS transistor by an isolation region therebetween;
forming a dummy region overlying the isolation region between the PMOS transistor and the second NMOS transistor;
depositing a compressive stress liner;
etching the compressive stress liner to remove the compressive stress liner from the first NMOS transistor, the second NMOS transistor, a portion of the isolation region between the PMOS transistor and the first NMOS transistor, and from a portion of the dummy region;
depositing a tensile stress liner overlying the compressive stress liner; and
etching the tensile stress liner to remove the tensile stress liner from a portion of the compressive stress liner and a portion of the dummy region.
7. The method of claim 6 wherein the step of forming a dummy region comprises the step of forming a dummy polycrystalline silicon region.
8. The method of claim 6 wherein the step of depositing a tensile stress liner comprises the step of depositing a tensile silicon nitride stress liner and wherein the step of depositing a compressive stress liner comprises the step of depositing a compressive silicon nitride stress liner.
9. A method of fabricating a stress enhanced CMOS circuit comprising a first NMOS transistor and a PMOS transistor separated by an isolation region and a second NMOS transistor spaced apart from the PMOS transistor, the method comprising the steps of:
forming a dummy region between the second NMOS transistor and the PMOS transistor;
depositing a compressive stress liner overlying the PMOS transistor but not the first NMOS transistor;
etching the compressive stress liner and leaving a remaining portion of the compressive stress liner overlying a first portion of the dummy region;
depositing a tensile stress liner overlying the first NMOS transistor and a portion but not the entirety of the compressive stress liner and a portion but not the entirety of the PMOS transistor; and
etching the tensile stress liner and leaving a remaining portion of the tensile stress liner overlying a second portion of the dummy region and spaced apart from the remaining portion of the compressive stress liner.
10. The method of claim 9 wherein the step of providing a compressive stress liner comprises the step of providing a compressive stress liner overlying a portion but not the entirety of the isolation region.
11. A method for fabricating a stress enhanced CMOS circuit comprising the steps of:
forming a first NMOS transistor and forming a second NMOS transistor;
forming a PMOS transistor adjacent the first NMOS transistor in a channel width direction and adjacent the second NMOS transistor in a channel length direction, the PMOS transistor and the first NMOS transistor separated by an isolation region therebetween;
depositing and patterning a dummy region positioned between the second NMOS transistor and the PMOS transistor;
depositing a compressive stress liner overlying the first NMOS transistor, the PMOS transistor, and the isolation region;
etching the compressive stress liner to remove the compressive stress liner from the first NMOS transistor and from a portion of the isolation region;
depositing a tensile stress liner overlying the first NMOS transistor, the PMOS transistor, and the isolation region; and
etching the tensile stress liner to remove a portion of the tensile stress liner overlying the compressive stress liner and leaving the tensile stress liner overlying the first NMOS transistor, the isolation region, and a portion of the compressive stress liner.
12. The method of claim 11 wherein the step of depositing a compressive stress liner comprises the step of depositing a first silicon nitride layer.
13. The method of claim 12 wherein the step of depositing a tensile stress liner comprises the step of depositing a second silicon nitride layer.
14. The method of claim 11 wherein the step of etching the compressive stress liner comprises the step of etching the compressive stress liner to leave a portion of the compressive stress liner overlying a portion of the dummy region and wherein the step of etching the tensile stress liner comprises the step of etching the tensile liner to leave a portion of the tensile stress liner overlying a portion of the dummy region and spaced apart from the portion of the compressive stress liner.
15. The method of claim 11 wherein the step of depositing and patterning a dummy region comprises the step of depositing and patterning a polycrystalline silicon dummy region.
16. The method of claim 11 wherein the step of etching the tensile stress liner comprises the step of selectively etching the tensile stress liner to leave a portion of the tensile stress liner overlying a portion of the PMOS transistor.
17. A method of fabricating a stress enhanced CMOS circuit comprising a first NMOS transistor and a PMOS transistor separated by an isolation region and a second NMOS transistor spaced apart from the PMOS transistor, the method comprising the steps of:
forming a dummy region between the second NMOS transistor and the PMOS transistor;
providing a compressive stress liner overlying the PMOS transistor but not the first NMOS transistor by depositing and etching the compressive stress liner and leaving a remaining portion of the compressive stress liner overlying a first portion of the dummy region; and
providing a tensile stress liner overlying the first NMOS transistor and a portion but not the entirety of the compressive stress liner by depositing and etching the tensile stress liner and leaving a remaining portion of the tensile stress liner overlying a second portion of the dummy region and spaced apart from the remaining portion of the compressive stress liner.
18. The method of claim 17 wherein the step of providing a compressive stress liner comprises the step of:
providing a compressive stress liner overlying the PMOS transistor but not the first NMOS transistor and overlying a portion but not the entirety of the isolation region by depositing and etching the compressive stress liner and leaving a remaining portion of the compressive stress liner overlying a first portion of the dummy region.