IP Library Granted Patent US 6,970,009
Granted Patent B1
US 6,970,009 · App. 10/759,917 · Granted Nov 29, 2005

Single-transistor two resistor circuit which translate test signals to selectable voltage levels

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Quick Facts
Patent No.
US 6,970,009
App. No.
10/759,917
Granted
Nov 29, 2005
Kind
B1
Abstract

A signal translator circuit, for use in sending test signals to an IC-chip in a chip testing system, includes first and second resistors, and a single transistor. The transistor has a current channel which is coupled in series with the first resistor between a source voltage terminal and an output terminal. The single transistor also has a control lead, for enabling and disabling the flow of current through the current channel, which receives an input test signal at voltage levels that are to be translated. The output terminal is coupled through the second resistor to a reference voltage terminal. The output terminal is also coupled to an input terminal of a socket which is structured to hold the IC-chip.

Claims (16)

1. A circuit, for use in testing an IC-module; said circuit comprising:

a single transistor having a current channel which is coupled in series with a first resistor between a source voltage terminal and an output terminal;

said single transistor also having a control lead, for enabling and disabling the flow of current through said current channel, which receives an input test signal;

a second resistor which couples said output terminal to a reference voltage terminal; and,

a socket which is structured to hold said IC-module, having a test signal input terminal that is coupled to said output terminal.

2. A circuit according to claim 1 wherein said first and second resistors have magnitudes which limit the square of said current through said current channel, times said first and second resistors, to be less than one-tenth of one watt.

3. A circuit according to claim 1 wherein said first resistor is connected directly to said source voltage terminal, and said current channel of said single transistor is connected directly to said output terminal.

4. A circuit according to claim 1 wherein said current channel of said single transistor is connected directly to said source voltage terminal, and said first resistor is connected directly to said output terminal.

5. A circuit according to claim 1 wherein said single transistor has a resistance through said current channel when said current is enabled which has a large tolerance, and said first and second resistors are substantially larger in resistance and have a small tolerance.

6. A circuit according to claim 1 which further includes a variable voltage source which has an output that is coupled to said source voltage terminal.

7. A circuit according to claim 1 wherein the only coupling between said output terminal and said second resistor is a conductor.

8. A circuit according to claim 1 wherein the only coupling between said output terminal and said second resistor is a conductor in a series with an inductive filter.

9. A circuit according to claim 1 wherein the only coupling between said output terminal and said test signal input terminal on said socket is a conductor and an input to one digital multiplexor.

10. A circuit according to claim 1 wherein the only coupling between said output-terminal and said test signal input terminal on said socket is a conductor and an input to one analog multiplexor.

11. A circuit according to claim 1 wherein said single transistor is an N-channel field effect transistor.

12. A circuit according to claim 1 wherein said single transistor is a P-channel field effect transistor.

Assignments (5)
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 047640, FRAME 0566 Recorded Mar 7, 2024
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS AGENT
To: DELTA DESIGN, INC.
Reel/Frame 066762/0857 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT STATEMENT THAT THIS DOCUMENT SERVES AS AN OATH/DECLARATION PREVIOUSLY RECORDED ON REEL 047640 FRAME 0566. ASSIGNOR(S) HEREBY CONFIRMS THE PATENT SECURITY AGREEMENT. Recorded Jan 2, 2019
From: DELTA DESIGN, INC.
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 048003/0306 →
PATENT SECURITY AGREEMENT Recorded Oct 1, 2018
From: DELTA DESIGN, INC.
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 047640/0566 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 18, 2006
From: UNISYS CORPORATION
To: DELTA DESIGN, INC.
Reel/Frame 017480/0927 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 16, 2004
From: OSTROWSKI, CARL LARRY; CARLSON, ROBERT HOWARD
To: UNISYS CORPORATION
Reel/Frame 014945/0767 →