Method of designing semiconductor integrated circuit with accurate capacitance extraction

1. A method of designing a semiconductor integrated circuit, comprising:

checking each border edge of a block area so as to determine whether a border edge is a first border edge where an external connection terminal is provided or a second border edge where no external connection terminal is provided;

providing a wiring prohibited area which extends a first distance from the first border edge and in which no wiring line running parallel to the first border edge exists;

providing a shielding line which is at a second distance from the second border edge and runs parallel to the second border edge;

determining a layout of the block area through floor planning, placement and routing;

extracting resistance and capacitance from the layout, for delay calculation and layout check, by utilizing the wiring prohibited area for the first border edge and the shielding line for the second border edge; and

completing a layout of the block area through the delay calculation and layout check.

2. The method as claimed in claim 1 , further comprising cutting out a physical block as said block area, said physical block being a layout area divided on a function-by-function basis at a top level in hierarchical layout designing.

3. The method as claimed in claim 1 , wherein said checking, providing a wiring prohibited area and providing a shielding line are repeated with respect to each wiring layer.

4. The method as claimed in claim 1 , wherein the first distance is longer than a minimum wiring distance.

5. The method as claimed in claim 1 , wherein the second distance is equal to a minimum wiring distance.