Memory with memory cells that include a MIM type capacitor with a lower electrode made for reduced resistance at an interface with a metal film
View Patent ↗A semiconductor device includes memory cells each having an MISFET for memory selection formed on one major surface of a semiconductor substrate and a capacitive element comprised of a lower electrode electrically connected at a bottom portion to one of a source and drain of the MISFET for memory selection via a first metal layer and an upper electrode formed on the lower electrode via a capacitive insulating film. The lower electrode has a thickness of 30 nm or greater at the bottom portion thereof. Sputtering with a high ionization ratio and high directivity, such as PCM, is adapted to the formation of the lower electrode to make only the bottom portion of a capacitor thicker.
1. A semiconductor device comprising memory cells each having an MISFET for memory selection formed on a major surface of a semiconductor substrate and a capacitive element comprised of a lower electrode electrically connected at a bottom portion to one of a source and drain of said MISFET for memory selection via a first metal layer and an upper electrode formed on said lower electrode via a capacitive insulating film,
wherein said lower electrode has a cup shape-provided along a side wall portion and a bottom portion of a hole provided in an interlayer insulating film and has a thickness of 30 nm or greater at the bottom portion of said lower electrode and a thickness of less than 30 nm at a side wall portion of said lower electrode.
2. The semiconductor device according to claim 1 , wherein said lower electrode is a metal film.
3. The semiconductor device according to claim 1 , wherein said lower electrode is a ruthenium film.
4. The semiconductor device according to claim 1 , wherein said capacitive insulating film is a tantalum oxide film.
5. The semiconductor device according to claim 1 , wherein said upper electrode is a ruthenium film.
6. The semiconductor device according to claim 1 , wherein said first metal layer is a titanium nitride film.
7. A semiconductor device comprising memory cells each having an MISFET for memory selection formed on a major surface of a semiconductor substrate and a capacitive element comprised of a lower electrode electrically connected at a bottom portion to one of a source and drain of said MISFET for memory selection via a first metal layer and a second metal layer and an upper electrode formed on said lower electrode via a capacitive insulating film,
wherein said lower electrode has a cup shape provided along a side wall portion and a bottom portion of a hole provided in an interlayer insulating film, said first metal layer and said second metal layer partly contact each other, said lower electrode is connected at an entire bottom of said lower electrode to said second metal layer and said lower electrode has a thickness of 30 nm or greater at the bottom portion of said lower electrode and a thickness of less than 30 nm at a side wall portion of said lower electrode.
8. The semiconductor device according to claim 7 , wherein said lower electrode is a metal film.
9. The semiconductor device according to claim 7 , wherein said lower electrode is a ruthenium film.
10. The semiconductor device according to claim 7 , wherein said capacitive insulating film is a tantalum oxide film.
11. The semiconductor device according to claim 7 , wherein said upper electrode is a ruthenium film.
12. The semiconductor device according to claim 7 , wherein said first metal layer is a titanium nitride film.