Stress-reduced layer system for use in storage capacitors
View Patent ↗The stress-reduced layer system has at least one first layer of polycrystalline or single-crystal semiconductor material, which adjoins a microcrystalline or amorphous, conducting or insulating second layer. The semiconductor layer is doped with at least two dopants of the same conductivity type, of which at least one is suitable for reducing mechanical stresses at the interface. The stress-reduced layer system, in a further embodiment, has at least one first layer of semiconductor material, conducting or insulating material and at least one conducting or insulating second layer. A further semiconductor layer, which is doped with at least one dopant that is suitable for reducing mechanical stresses at the interface between the second layer and the first layer, is arranged between the first layer and the second layer or it is applied to the surface of the first layer or the second layer that is opposite from the interface.
1. A storage capacitor, comprising:
a substrate having a trench formed therein, said trench having sidewalls, a bottom, an upper portion and a lower portion;
a collar disposed at said sidewalls in said upper portion of said trench;
a lower capacitor electrode;
a storage dielectric disposed at said sidewalls of said lower portion of said trench, at said bottom of said trench and at said collar in said upper portion of said trench;
an upper capacitor electrode being a conductive layer disposed at said storage dielectric in said lower portion of said trench, said conductive layer being formed of a material selected from the group consisting of metal silicide, metal nitride, metal carbide, WN, WSiN, WC, TiN, TaN, and TaSiN;
a doped layer selected from the group consisting of a SiGe layer, a SiC layer, and a GaAs layer or a doped filling selected from the group consisting of a SiGe filling, a SiC filling, and a GaAs filling disposed on a side of said conductive layer remote from said storage dielectric and said doped layer or said doped filling covering said upper capacitor electrode and being disposed at said storage dielectric at said upper portion of said trench;
said storage dielectric being disposed between said collar and said doped layer or said doped filling in said upper portion of said trench; and
said doped layer or said doped filling being suitably doped to reduce an interfacial stress between said storage dielectric and said conductive layer.
2. The storage capacitor according to claim 1 , configured to form a part of a DRAM memory cell.
3. The storage capacitor according to claim 1 , wherein a dopant for said SiGe layer is selected from the group consisting of Al, Ga, In, Tl, B, As, Sb, and P.
4. The storage capacitor according to claim 1 , wherein said storage dielectric contains a material selected from the group consisting of silicon nitride, silicon dioxide, silicon oxynitride, metal oxide, aluminum oxide, Pr 2 O 3 , Nd 2 O 3 , Al 2 O 3 with an addition of Hf, Zr, Y or La.
5. The storage capacitor according to claim 1 , wherein said doped layer has a dopant distribution with a gradient.