Synchronization module
View Patent ↗Systems and methods are described for a core sync module. A method includes receiving a pair of input clock signals; utilizing a stratum clock state machine to control a multiplexer; utilizing the multiplexer to switch an input of a main clock between each of the pair of input clock signals; inducing a phase build-out activity; and transmitting an output clock signal. An apparatus includes a first input clock digital phase-locked loop; a second input clock digital phase-locked loop; a stratum clock state machine coupled to the first input clock digital phase-locked loop and to the second input clock digital phase-locked loop; and a main clock phase-locked loop coupled to the first input clock digital phase-locked loop, to the second input clock digital phase-locked and to the stratum clock state machine.
1. An apparatus, comprising:
a first input clock digital phase-locked loop;
a second input clock digital phase-locked loop;
a stratum clock state machine coupled to the first input clock digital phase-locked loop and to the second input clock digital phase-locked loop;
a main clock phase-locked loop coupled to the first input clock digital phase-locked loop, to the second input clock digital phase-locked loop and to the stratum clock state machine; and
a numerically controlled oscillator coupled to the main clock phase-locked loop.
2. The apparatus of claim 1 , wherein the stratum clock state machine defines a holdover state in which a phase buildout function is active.
3. The apparatus of claim 2 , wherein the stratum clock state machine defines a normal state, an offset state, a switch state and a freerun state.
4. The apparatus of claim 1 , further comprising a phase and frequency detector coupled to the numerically controlled oscillator.
5. The apparatus of claim 4 , further comprising an oven controlled crystal oscillator, coupled to the phase and frequency detector.
6. The apparatus of claim 5 , further comprising a temperature sensor coupled to the oven controlled crystal oscillator and to the stratum clock state machine.
7. The apparatus of claim 4 , further comprising a loop filter coupled to the phase and frequency detector.
8. The apparatus of claim 7 , wherein the loop filter includes a programmable filter.
9. The apparatus of claim 8 , wherein the programmable filter is coupled to the stratum clock state machine.
10. The apparatus of claim 7 , further comprising a voltage controlled oscillator coupled to the loop filter, to the first input clock digital phase-locked loop and to the second input clock digital phase-locked loop.
11. The apparatus of claim 10 , further comprising:
an output buffer coupled to the voltage controlled oscillator; and
a clock divider coupled to the voltage controlled oscillator and to the output buffer.
12. The apparatus of claim 1 , further comprising an eight bit parallel bus coupled to the stratum clock state machine.
13. The apparatus of claim 1 , further comprising a logic interface coupled to the stratum clock state machine.