Fabrication method of semiconductor wafer
View Patent ↗A fabrication method of a semiconductor wafer can fill trenches formed in a semiconductor substrate with an epitaxial film with high crystal quality without leaving cavities in the trenches. The trenches are formed in the first conductivity type semiconductor substrate. Planes exposed inside the trenches are made clean surfaces by placing the substrate in a gas furnace, followed by supplying the furnace with an etching gas and carrier gas, and by performing etching on the exposed planes inside the trenches by a thickness from about a few nanometers to one micrometer. The trenches have a geometry opening upward through the etching. Following the etching, a second conductivity type semiconductor is epitaxially grown in the trenches by supplying the furnace with a growth gas, etching gas, doping gas and carrier gas, thereby filling the trenches. Instead of making the trenches slightly-opened upward, their sidewalls may be made planes enabling facet formation.
1. A fabrication method of a semiconductor wafer comprising the steps of:
forming trenches with a pattern in a surface layer of a first conductivity type semiconductor substrate;
performing, in a gas furnace, etching on exposed planes inside the trenches by supplying etching gas into the gas furnace; and
filling the trenches by epitaxially growing a second conductivity type semiconductor in the trenches after completing the etching,
wherein the step of filling carries out the epitaxial growth by setting crystal plane orientations of sidewalls of the trenches at orientations that enable facet formation, and by simultaneously or alternately supplying the gas furnace with etching gas and growth gas for accelerating the epitaxial growth of the second conductivity type semiconductor.
2. The fabrication method of a semiconductor wafer as claimed in claim 1 , wherein the step of etching performs the etching by setting the pressure of a carrier gas at a value equal to or greater than 100 Torr and equal to or less than 760 Torr.
3. The fabrication method of a semiconductor wafer as claimed in claim 1 , wherein the growth gas is a dichlorosilane gas.
4. The fabrication method of a semiconductor wafer as claimed in claim 1 , wherein the step of etching performs the etching on the exposed planes inside the trenches such that widths of openings of the trenches become greater than widths of bottoms of the trenches.