Digital visual interface
Techniques or designs of circuits to correct distortions in signals transported over a high-speed digital connection between a video source (e.g., a PC or a DVD player) and a digital monitors (such as LCDs) are disclosed. According to one aspect of the present invention, a distorted signal is corrected by an interface circuit that oversamples the incoming signal with clock pulses or signals generated using a phase lock loop (PLL) from a clock seed signal. These clock signals possess different phases that are shifted from each other. In order to support a wide range of data rate, a programmable DPLL is used to produce a number of different ranges of clock frequency (e.g., 4 ranges). In addition, to avoid data phase shift, a delay locked loop (DLL) is used to compensate for the phase shift. A phase detection logic is also used to extract phase information from the over-sampled data. The phase information is fed back to the DLL.
1. An integrated circuit comprising:
an input circuit configured to receive a channel signal from a source, provide impedance matching and amplify the channel signal;
a clock generator configured to generate a plurality of clock signals with a substantially identical frequency and a phase shift in reference to an initial clock signal, wherein the initial clock signal is provided in accordance with a frequency in the channel signal;
an oversampling circuit configured to sample the channel signal in response to the plurality of clock signals;
a phase detection unit configured to receive sampled signals from the oversampling circuit and generate a first adjustment signal and a second adjustment signal according to a predetermined mapping relationship; and
a phase alignment circuit configured to adjust the phases of the plurality of the clock signals in response to the first adjustment signal and the second adjustment signal, wherein the phase alignment circuit comprises a delay locked loop configured (i) to receive the plurality of clock signals from the clock generator, (ii) to adjust the phases of the plurality of clock signals in response to an offset signal and (iii) to present the phase adjusted plurality of clock signals to the oversampling circuit, wherein the offset signal is generated in response to the first adjustment signal and the second adjustment signal.
2. The integrated circuit of claim 1 , wherein the phase detection unit comprises:
a logic circuit coupled to the oversampling circuit and configured to generate a plurality of detection signals in response to the sampled signals; and
a decision circuit configured to generate the first adjustment signal and the second adjustment signal in response to the plurality of detection signals and a clock signal.
3. The integrated circuit of claim 1 , wherein the oversampling circuit, the phase detection unit, and the phase alignment circuit form a feedback loop configured to adjust the phases of all of the plurality of clock signals.
4. The integrated circuit of claim 2 , wherein the logic circuit comprises a plurality of Exclusive-OR gates configured to receive the sampled signals and present the plurality of detection signals.
5. The integrated circuit of claim 1 , further including a counter coupled between the phase detection unit and the phase alignment circuit, wherein the counter is configured to generate the offset signal in response to the first adjustment signal and the second adjustment signal.
6. The integrated circuit of claim 2 , wherein the decision circuit comprises a mapping table providing the mapping relationship from the plurality of detection signals to the first adjustment signal and the second adjustment signal.
7. The integrated circuit of claim 6 , wherein, depending on the first adjustment signal and the second adjustment signal, the adjustment is zero, a downward adjustment or an upward adjustment to the phases of the plurality of clock signals.
8. The integrated circuit of claim 1 , wherein the clock generator works in conjunction with a phase lock loop.
9. The integrated circuit of claim 8 , wherein the phase lock loop is one of a programmable PLL or a digital phase lock loop circuit.
10. An integrated circuit comprising (i) at least three channel data processing units configured to receive three input signals representing a video signal and (ii) a clock generator configured to generate a plurality of clock signals with a substantially identical frequency and a phase shift in reference to an initial clock signal, wherein the initial clock signal is provided in accordance with a frequency associated with the three input signals and each of the three channel data processing units are configured to process a respective one of the three input signals and include:
an input circuit configured to receive the respective input signal, provide impedance matching and amplify the respective input signal;
an oversampling circuit configured to sample the respective input signal in response to the plurality of clock signals;
a phase detection unit configured to receive sampled signals from the oversampling circuit and generate a first adjustment signal and a second adjustment signal according to a predetermined mapping relationship; and
a phase alignment circuit configured to adjust the phases of the plurality of clock signals in response to the first adjustment signal and the second adjustment signal, wherein the phase alignment circuit comprises a delay locked loop configured (i) to receive the plurality of clock signals from the clock generator, (ii) to adjust the phases of the plurality of clock signals in responses to an offset signal and (iii) to present the phase adjusted plurality of clock signals to the oversampling circuit, wherein the offset signal is generated in response to the first adjustment signal and the second adjustment signal.
11. The integrated circuit of claim 10 , wherein the phase detection unit comprises:
a logic circuit coupled to the oversampling circuit and configured to generate a plurality of detection signals in response to the sampled signals; and
a decision circuit configured to generate the first adjustment signal and the second adjustment signal in response to the plurality of detection signals and a clock signal.
12. The integrated circuit of claim 10 , wherein the oversampling circuit, the phase detection unit, and the phase alignment circuit form a feedback loop configured to adjust the phases of all of the plurality of clock signals.
13. The integrated circuit of claim 11 , wherein the logic circuit comprises a plurality of Exclusive-OR gates configured to receive the sampled signals and present the plurality of detection signals.
14. The integrated circuit of claim 10 , wherein each channel data processing unit further includes a counter coupled between the phase detection unit and the phase alignment circuit, wherein the counter is configured to generate the offset signal in response to the first adjustment signal and the second adjustment signal.
15. The integrated circuit of claim 11 , wherein the decision circuit comprises a mapping table providing the mapping relationship from the plurality of detection signals to the first adjustment signal and the second adjustment signal.
16. The integrated circuit of claim 15 , wherein, depending on the first adjustment signal and the second adjustment signal, the adjustment is zero, a downward adjustment or an upward adjustment to the phases of the plurality of clock signals.
17. The integrated circuit of claim 10 , wherein the clock generator works in conjunction with a phase lock loop.
18. The integrated circuit of claim 17 , wherein the phase lock loop is one of a programmable PLL or a digital phase lock loop circuit.