IP Library Granted Patent US 7,217,612
Granted Patent B2
US 7,217,612 · App. 10/809,011 · Granted May 15, 2007

Manufacturing method for a semiconductor device with reduced local current

Assignee: Sanyo Electric Co., Ltd.
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,217,612
App. No.
10/809,011
Granted
May 15, 2007
Kind
B2
Abstract

A semiconductor device including: a first gate insulating film which is pattern-formed on an N type well region within a P type semiconductor substrate; a second gate insulating film which is formed on the semiconductor substrate except for this first gate insulating film; a gate electrode, which is formed in such a manner that this gate electrode is bridged over the first gate insulating film and the second gate insulating film; a P type body region which is formed in such a manner that this P type body region is located adjacent to the gate electrode; an N type source region and a channel region, which are formed within this P type body region; and an N type drain region which is formed at a position separated from the P type body region.

Claims (19)

1. A method for manufacturing a semiconductor device, comprising the steps of:

forming a body region by implanting to diffuse an impurity in a predetermined region of a semiconductor layer;

after field-oxidizing a surface region of said semiconductor layer by way of the LOCOS method to form an insulating film, forming a first gate insulating film by patterning said insulating film while a resist film formed on a predetermined region of said insulating film is employed as a mask;

forming a second gate insulating film on said semiconductor layer other than said first gate insulating film, and then forming a gate electrode so that said gate electrode is bridged over said first gate insulating film and said second gate insulating film; and

forming a source region and drain region by implanting an impurity of an opposite conductive type to said body region into both a source forming region formed within said body region and a drain forming region formed within said semiconductor layer while a resist film having an opening is employed as a mask, wherein said first gate insulating film is not formed at a position lower than at least a surface position of said semiconductor layer in the step of forming said first gate insulating film.

2. The semiconductor device manufacturing method as claimed in claim 1 , wherein a device separation film is formed in the same step of forming said first gate insulating film.

3. A method for manufacturing a semiconductor device, comprising the steps of:

forming a body region by implanting to diffuse an impurity in a predetermined region of a semiconductor layer;

after field-oxidizing a surface region of said semiconductor layer by way of the LOCOS method to form an insulating film, forming a first gate insulating film by patterning said insulating film while a resist film formed on a predetermined region of said insulating film is employed as a mask;

forming a second gate insulating film on said semiconductor layer other than said first gate insulating film, and then forming a sate electrode so that said gate electrode is bridged over said first sate insulating film and said second gate insulating film; and

forming a source region and drain region by implanting an impurity of an opposite conductive type to said body region into both a source forming region formed within said body region and a drain forming region formed within said semiconductor layer while a resist film having an opening is employed as a mask , wherein, in the step of forming the first gate insulating film, said first gate insulating film is not formed at a position lower than a surface position of said semiconductor layer so that local current crowding is not produced between at least an edge portion of said body region and an edge portion of said first gate insulating film.

4. A method for manufacturing a semiconductor device, comprising the steps of:

forming a body region by implanting to diffuse an impurity in a predetermined region of a semiconductor layer;

after field-oxidizing a surface region of said semiconductor layer by way of the LOCOS method to form an insulating film, forming a first sate insulating film by patterning said insulating film while a resist film formed on a predetermined region of said insulating film is employed as a mask;

forming a second gate insulating film on said semiconductor layer other than said first gate insulating film, and then forming a sate electrode so that said sate electrode is bridged over said first gate insulating film and said second gate insulating film; and

forming a source region and drain region by implanting an impurity of an opposite conductive type to said body region into both a source forming region formed within said body region and a drain forming region formed within said semiconductor layer while a resist film having an opening is employed as a mask wherein the first gate insulating film is not formed at a position lower than at least a surface position of the source region and the drain region, in the step of forming said first gate insulating film.

5. The semiconductor device manufacturing method according to claim 1 wherein the first gate insulating film is not formed at a position lower than at least a surface position of the source region and the drain region, in the step of forming said first gate insulating film.

6. The semiconductor device manufacturing method as claimed in claim 3 , wherein a device separation film is formed in the same step of forming said first gate insulating film.

7. The semiconductor device manufacturing method as claimed in claim 4 , wherein a device separation film is formed in the same step of forming said first gate insulating film.

Assignments (6)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 038620, FRAME 0087 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PATENT NUMBER 5859768 AND TO RECITE COLLATERAL AGENT ROLE OF RECEIVING PARTY IN THE SECURITY INTEREST PREVIOUSLY RECORDED ON REEL 038620 FRAME 0087. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Aug 25, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 039853/0001 →
SECURITY INTEREST Recorded Apr 15, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 038620/0087 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT #12/577882 PREVIOUSLY RECORDED ON REEL 026594 FRAME 0385. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded May 6, 2014
From: SANYO ELECTRIC CO., LTD
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 032836/0342 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 14, 2011
From: SANYO ELECTRIC CO., LTD.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 026594/0385 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 11, 2007
From: NISHIBE, EIJI; KIKUCHI, SHUICHI
To: SANYO ELECTRIC CO., LTD.
Reel/Frame 019145/0977 →
Priority Claims (1)
JP P 2000-372228 · Dec 7, 2000 · national
Continuity (2)
Division 1000738400 · Oct 22, 2001
Related Publication 20040178459A1 · Sep 16, 2004