IP Library Granted Patent US 7,202,687
Granted Patent B2
US 7,202,687 · App. 10/820,319 · Granted Apr 10, 2007

Systems and methods for wireless semiconductor device testing

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Quick Facts
Patent No.
US 7,202,687
App. No.
10/820,319
Granted
Apr 10, 2007
Kind
B2
Abstract

A base controller disposed in a test cassette receives test data for testing a plurality of electronic devices. The base controller wirelessly transmits the test data to a plurality of wireless test control chips, which write the test data to each of the electronic devices. The wireless test control chips then read response data generated by the electronic devices, and the wireless test control chips wirelessly transmit the response data to the base controller.

Claims (38)

1. A testing apparatus comprising:

a base controller comprising a plurality of first connectors that are connectable to a tester;

a plurality of test controllers, each said test controller electrically connected to a plurality of second connectors that are electrically connectable to an electronic device; and

wireless means for communicating test data wirelessly between said base controller and said test controllers.

2. The apparatus of claim 1 , wherein at least a portion of one of said test controllers is disposed on said electronic device.

3. The apparatus of claim 1 further comprising

an enclosure that is sealable, at least one of said base controller, test controller, or wireless means disposed within said enclosure.

4. The apparatus of claim 1 , wherein said electronic device comprises a semiconductor die.

5. The apparatus of claim 1 further comprising a plurality of said electronic devices, and wherein each said electronic device comprises a semiconductor die, and said dies compose an unsingulated semiconductor wafer.

6. The apparatus of claim 1 , wherein said wireless means comprises a first transceiver electrically connected to said test controller and second transceivers electrically connected to said base controller.

7. The apparatus of claim 1 , wherein said second connectors comprise a plurality of probes, each disposed to contact a terminal of said electronic device.

8. The apparatus of claim 1 , wherein said test data includes at least one of test vectors or test commands.

9. The apparatus of claim 1 , wherein said base controller comprises processing circuitry.

10. The apparatus of claim 9 , wherein said processing circuitry comprises a microprocessor.

11. The apparatus of claim 1 , wherein said base controller receives said test data and controls transmission of said test data through said wireless means to a multiplicity of said test controllers.

12. The apparatus of claim 1 , wherein each said test controller comprises processing circuitry.

13. The apparatus of claim 12 , wherein said processing circuitry comprises a microprocessor.

14. The apparatus of claim 1 , wherein each said test controller controls writing of test data to at least one electronic device to be tested.

15. The apparatus of claim 14 , wherein each said test controller further controls reading of response data from said at least one electronic device.

16. The apparatus of claim 15 , wherein each said test controller further analyzes said response data.

17. A test system comprising:

a tester;

a test station;

a communications link between said tester and said test station; and

a substrate disposed in said test station, said substrate comprising:

a base controller in communication with said communications link;

a plurality of test controllers each electrically connected to a plurality of connectors that are electrically connectable to one of a plurality of electronic devices to be tested; and

wireless means for communicating test data wirelessly between said base controller and said plurality of test controllers.

18. The test system of claim 17 , wherein at least a portion of one of said test controllers is disposed on one of said electronic devices.

19. The test system of claim 17 , wherein said connectors comprise a plurality of probes, each disposed to contact a terminal of one of said electronic devices.

20. The test system of claim 17 further comprising a plurality of said testers, each in communication with said communications link.

21. The test system of claim 20 further comprising a plurality of said test stations, each in communication with said communications link.

22. The test system of claim 21 , wherein said electronic devices are semiconductor dies.

23. The test system of claim 22 , wherein said semiconductor dies compose an unsingulated semiconductor wafer.

24. The test system of claim 17 , wherein said test data includes at least one of test vectors or test commands.

25. The test system of claim 17 further comprising a cassette in which said substrate is disposed.

26. The test system of claim 25 , wherein said cassette is hermetically sealable.

27. The test system of claim 17 , wherein said substrate composes a probe card.

Assignments (4)
RELEASE OF SECURITY INTEREST Recorded Aug 7, 2025
From: HSBC BANK USA, NATIONAL ASSOCIATION
To: FORMFACTOR, INC.
Reel/Frame 072853/0001 →
SECURITY INTEREST Recorded Jul 29, 2025
From: FORMFACTOR, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS ADMINISTRATIVE AGENT
Reel/Frame 072263/0272 →
SECURITY INTEREST IN UNITED STATES PATENTS AND TRADEMARKS Recorded Jul 12, 2016
From: FORMFACTOR, INC.; ASTRIA SEMICONDUCTOR HOLDINGS, INC.; CASCADE MICROTECH, INC.; MICRO-PROBE INCORPORATED
To: HSBC BANK USA, NATIONAL ASSOCIATION
Reel/Frame 039184/0280 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 8, 2004
From: KHANDROS, IGOR Y.; ELDRIDGE, BENJAMIN N.; MILLER, CHARLES A.; SPORCK, NICHOLAS
To: FORMFACTOR, INC.
Reel/Frame 015200/0464 →