IP Library Granted Patent US 7,222,280
Granted Patent B1
US 7,222,280 · App. 10/825,409 · Granted May 22, 2007

Diagnostic process for automated test equipment

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Quick Facts
Patent No.
US 7,222,280
App. No.
10/825,409
Granted
May 22, 2007
Kind
B1
Abstract

A test apparatus including a means for sending a first test pattern to a device under test (DUT), where the first test pattern is a part of a planned sequence of tests, and further including a means for evaluating the test results received from the DUT, and a method of testing are described. The test results may include anomalous data indicative of a defect in the DUT. If so, a second test pattern that is not part of the planned sequence of tests is selected. The second test pattern is selected based on a diagnosis of the anomalous data by the test apparatus.

Claims (29)

1. In a test apparatus, a method of testing a device, said method comprising:

sending a first test pattern to a device under test (DUT), said first test pattern part of a planned sequence of tests, wherein a first test is executed using said first test pattern;

evaluating test results for said first test and received from said DUT, said test results comprising anomalous data indicative of a defect in said DUT;

automatically selecting a second test pattern that is not part of said planned sequence of tests, wherein said second test pattern is selected based on a diagnosis of said anomalous data by said test apparatus, wherein said diagnosis is performed by recognizing a pattern in said anomalous data, wherein said second test pattern is selected according to said pattern in said anomalous data; and

sending said second test pattern to said DUT, wherein a second test is executed using said second test pattern.

2. The method of claim 1 wherein only said anomalous data is saved and evaluated by said test apparatus.

3. The method of claim 1 wherein said test apparatus comprises a plurality of pins for receiving signals from said DUT, wherein at least one of said signals includes said test results.

4. The method of claim 3 wherein said test results received on said one of said pins are conditionally captured and stored in response to a signal received on another of said pins.

5. The method of claim 3 wherein said test results are conditionally captured and stored in response to said test apparatus recognizing a begin sequence of one or more bits received from said DUT.

6. The method of claim 5 wherein capture and storage of said test results are ended in response to said test apparatus recognizing an end sequence of one or more bits received from said DUT.

7. The method of claim 1 wherein said second test pattern is selected from a plurality of precomputed test patterns.

8. An automated test system comprising:

a test controller; and

a test instrument coupled to said test controller, wherein said test instrument sends a first test pattern to a device under test (DUT) that executes a first test using said first test pattern, said first test pattern part of a planned sequence of tests, evaluates test results for said first that are received from said DUT, said test results comprising anomalous data indicative of a defect in said DUT, and automatically selects a second test pattern that is not part of said planned sequence of tests, wherein said second test pattern is selected based on a diagnosis of said anomalous data by said test instrument, wherein said diagnosis is performed by recognizing a pattern in said anomalous data, wherein said second test pattern is selected according to said pattern in said anomalous data, wherein said second test pattern is sent to said DUT, and wherein a second test is executed using said second test pattern.

9. The automated test system of claim 8 wherein only said anomalous data is saved and evaluated by said test instrument.

10. The automated test system of claim 8 wherein said test instrument comprises a plurality of pins for receiving signals from said DUT, wherein at least one of said signals includes said test results.

11. The automated test system of claim 8 wherein said test results received on said one of said pins are conditionally captured and stored in response to a signal received on another of said pins.

12. The automated test system of claim 8 wherein said test results are conditionally captured and stored in response to said test instrument recognizing a begin sequence of one or more bits received from said DUT.

13. The automated test system of claim 12 wherein capture and storage of said test results are ended in response to said test instrument recognizing an end sequence of one or more bits received from said DUT.

14. The automated test system of claim 8 wherein said second test pattern is selected from a plurality of precomputed test patterns.

15. An automated test system comprising:

means for sending a first test pattern to a device under test (DUT), said first test pattern part of a planned sequence of tests, wherein a first test is executed using said first test pattern;

means for evaluating test results for said first test that are received from said DUT, said test results comprising anomalous data indicative of a defect in said DUT; and

means for automatically selecting a second test pattern that is not part of said planned sequence of tests, wherein said second test pattern is selected based on a diagnosis of said anomalous data by said test apparatus, wherein said diagnosis is performed by recognizing a pattern in said anomalous data, wherein said second test pattern is selected according to said pattern in said anomalous data, wherein said means for sending then sends said second test pattern to said DUT, and wherein a second test is executed using said second test pattern.

16. The automated test system of claim 15 wherein only said anomalous data is saved and evaluated.

17. The automated test system of claim 15 wherein said test results are conditionally captured and stored in response to a signal received from said DUT.

18. The automated test system of claim 15 wherein said test results are conditionally captured and stored in response to a begin sequence of one or more bits received from said DUT.

19. The automated test system of claim 18 wherein capture and storage of said test results are ended in response to an end sequence of one or more bits received from said DUT.

20. The automated test system of claim 15 wherein said second test pattern is selected from a plurality of precomputed test patterns.

Assignments (8)
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS, RECORDED AT REEL 047185, FRAME 0624 Recorded Mar 7, 2024
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS AGENT
To: XCERRA CORPORATION
Reel/Frame 066762/0811 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT STATEMENT THAT THIS DOCUMENT SERVES AS AN OATH/DECLARATION PREVIOUSLY RECORDED ON REEL 047185 FRAME 0628. ASSIGNOR(S) HEREBY CONFIRMS THE PATENT SECURITY AGREEMENT. Recorded Nov 28, 2018
From: XCERRA CORPORATION
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 047675/0354 →
PATENT SECURITY AGREEMENT Recorded Oct 2, 2018
From: XCERRA CORPORATION
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 047185/0624 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PATENT NUMBER 7261561 AND REPLACE WITH PATENT NUMBER 7231561 PREVIOUSLY RECORDED ON REEL 034660 FRAME 0188. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT. Recorded Feb 11, 2016
From: XCERRA CORPORATION; EVERETT CHARLES TECHNOLOGIES LLC
To: SILICON VALLEY BANK, AS ADMINISTRATIVE AGENT
Reel/Frame 037824/0372 →
SECURITY AGREEMENT Recorded Dec 18, 2014
From: XCERRA CORPORATION; EVERETT CHARLES TECHNOLOGIES LLC
To: SILICON VALLEY BANK, AS ADMINISTRATIVE AGENT
Reel/Frame 034660/0188 →
RELEASE OF SECURITY INTEREST IN UNITED STATES PATENTS Recorded Dec 18, 2014
From: SILICON VALLEY BANK, AS ADMINISTRATIVE AGENT
To: XCERRA CORPORATION; EVERETT CHARLES TECHNOLOGIES LLC
Reel/Frame 034660/0394 →
CHANGE OF NAME Recorded May 27, 2014
From: LTX-CREDENCE CORPORATION
To: XCERRA CORPORATION
Reel/Frame 033032/0768 →
SECURITY AGREEMENT Recorded Jan 17, 2014
From: LTX-CREDENCE CORPORATION; EVERETT CHARLES TECHNOLOGIES LLC
To: SILICON VALLEY BANK, AS ADMINISTRATIVE AGENT
Reel/Frame 032086/0476 →