Wiring tape for semiconductor device including a buffer layer having interconnected foams
View Patent ↗In a semiconductor device having a three-layered buffer layer comprising core layer 1 having interconnected foams such as a three-dimensional reticular structure and adhesive layers 2 provided on both sides of the core layer as a stress buffer layer between semiconductor chip 5 and wiring 4 to lessen a thermal stress generated between the semiconductor device and the package substrate, where a thickness ratio of the core layer 1 to total buffer layer is at least 0.2, the production process can be simplified by using such a buffer layer, thereby improving the mass production capacity and enhancing the package reliability.
1. A wiring tape for a semiconductor device, which comprises a wiring layer comprising an insulating layer and a wiring on the insulating layer, one end of the wiring being connected to terminals on a semiconductor chip and the other end of the wiring being connected to external terminals for connecting to a package substrate; and a three-layered buffer elastomer layer bonded to a wiring-formed side of the wiring layer, the buffer elastomer layer comprising a structure having interconnected foams or a three-dimensional reticular structure, an adhesive layer provided on the semiconductor chip-facing side of the structure having interconnected foams or the three-dimensional reticular structure, to bond to the semiconductor chip and another adhesive layer provided on the other side of the structure, to bond to the wiring-formed side of the wiring layer to relax thermal stress generated between the semiconductor chip and the package substrate during heating.
2. A wiring tape according to claim 1 , wherein a thickness ratio of the structure having interconnected foams or the three-dimensional reticular structure to total buffer layer thickness is at least 0.2 to reduce the likelihood of failure of the semiconductor device during heating performed in a reflow operation used in manufacturing the semiconductor device.
3. A wiring tape according to claim 1 , wherein the buffer layer is comprised of a laminate prepared by pasting both sides of the structure having interconnected foams or the three-dimensional reticular structure with the adhesive layers, respectively.
4. A wiring tape according to claim 1 , wherein the buffer layer is composed of a laminate prepared by pasting both sides of the structure having interconnected foams with adhesive layers each comprising a structure having interconnected foams whose pores are filled with an adhesive, respectively.
5. A wiring tape according to claim 1 , wherein the adhesive layer on the semiconductor chip-facing side is directly bonded to the semiconductor chip and the other adhesive layer is directly bonded to the wiring-formed side of the wiring layer.
6. A wiring tape for a semiconductor device, which comprises a wiring layer comprising an insulating layer and a wiring on the insulating layer, one end of the wiring being connected to terminals on a semiconductor chip and the other end of the wiring being connected to external terminals for connecting to a package substrate; and means for relaxing thermal stress generated between the semiconductor chip and the package substrate and for releasing steam pressure generated during heating in a reflow operation used in forming a package, including the wiring tape and the semiconductor device, to outside of the package, said means comprising:
a three-layered buffer elastomer layer bonded to a wiring-formed side of the wiring layer, the buffer elastomer layer comprising a structure having interconnected foams or a three-dimensional reticular structure, an adhesive layer provided on the semiconductor chip-facing side of the structure having interconnected foams or the three-dimensional reticular structure, to bond to the semiconductor chip and another adhesive layer provided on the other side of the structure, to bond to the wiring-formed side of the wiring layer.
7. A wiring tape according to claim 6 , wherein a thickness ratio of the structure having interconnected foams or the three-dimensional reticular structure to total buffer layer thickness is at least 0.2 to reduce the likelihood of failure of the semiconductor device during heating performed in a reflow operation used in manufacturing the semiconductor device.
8. A wiring tape according to claim 6 , wherein the buffer layer is comprised of a laminate prepared by pasting both sides of the structure having interconnected foams or the three-dimensional reticular structure with the adhesive layers, respectively.
9. A wiring tape according to claim 6 , wherein the adhesive layer on the semiconductor chip-facing side is directly bonded to the semiconductor chip and the other adhesive layer is directly bonded to the wiring-formed side of the wiring layer.