Closed-grid bus architecture for wafer interconnect structure
View Patent ↗An interconnect structure employs a closed-grid bus to link an integrated circuit tester channel to an array of input/output (I/O) pads on a semiconductor wafer so that the tester channel can concurrently communicate with all of the I/O pads. The interconnect structure includes a circuit board implementing an array of bus nodes, each corresponding to a separate one of the I/O pads. The circuit board includes at least two layers. Traces mounted on a first layer form a set of first daisy-chain buses, each linking all bus nodes of a separate row of the bus node array. Traces mounted on a second circuit board layer form a set of second daisy-chain buses, each linking all bus nodes of a separate column of the bus node array. Vias and other circuit board interconnect ends of the first and second daisy-chain buses so that they form the closed-grid bus. Each bus node is connected though a separate isolation resistor to a separate contact pad mounted on a surface of the circuit board. A set of spring contacts or probes link each contact pad to a separate one of the I/O pads on the wafer.
1. An apparatus for providing electrically conductive paths for test signals, said apparatus comprising:
a substrate comprising a first surface and a second surface opposite said first surface;
a plurality of electrically conductive terminals disposed on said first surface of said substrate;
a plurality of electrically conductive signal paths within said substrate, ones of said signal paths being electrically connected to ones of said terminals;
a plurality of electrically conductive probes attached to said second surface of said substrate, said probes disposed to contact respective individual ones of a plurality of electronic devices to be tested; and
a thin film resistor electrically connecting one of said signal paths with one of said probes, said one of said signal paths also being electrically interconnected to other of said probes, said resistor thereby isolating said other of said probes from a fault in one of said electronic devices contacted by said one of said probes, wherein said one of said signal paths is part of a bus structure that electrically connects one of said terminals to ones of said probes, said bus structure providing a plurality of different conductive paths between said one of said terminals and at least one of said probes.
2. The apparatus of claim 1 further comprising a plurality of resistors, ones of said resistors electrically connecting ones of said signal paths with ones of said probes.
3. The apparatus of claim 2 , wherein said resistors are thin film resistors.
4. The apparatus of claim 1 further comprising a plurality of resistors, wherein ones of said resistors electrically connect said one of said signal paths with ones of said probes.
5. The apparatus of claim 4 , wherein said resistors are thin film resistors.
6. The apparatus of claim 1 , wherein said terminals are configured to make connections with a tester configured to control testing of said electronic device.
7. The apparatus of claim 1 , wherein said probes comprise spring contact structures.
8. The apparatus of claim 1 , said bus structure comprising at least one closed conductive loop.
9. The apparatus of claim 1 , wherein:
said substrate comprises a plurality of layers of electrically insulative material; said bus structure comprising:
a conductive first via electrically connected to said one of said terminals and passing through a first of said layers of said substrate; and
a plurality of conductive second vias passing through a second of said layers of said substrate,
wherein said first via is electrically connected to said second vias.