Granted Patent B1

US 7,279,735 · App. 10/838,215 · Granted Oct 9, 2007

Abstract

Claims (34)

1. A memory device, comprising:

a substrate;

an insulating layer formed on the substrate;

a fin structure formed on the insulating layer, the fin structure comprising a first portion comprising silicon-germanium and a second portion comprising a strained silicon layer disposed on the first portion;

a semiconducting layer formed over the fin structure, the semiconducting layer acting as a floating gate for the memory device;

a dielectric layer formed on the semiconducting layer, the dielectric layer acting as an inter-gate dielectric for the memory device; and

a control gate formed on the gate dielectric layer.

2. The memory device of claim 1 , wherein the first portion of the fin structure has a thickness ranging from about 300 Å to about 500 Å and the second portion of the fin structure has a thickness ranging from about 150 Å to about 250 Å.

3. The memory device of claim 1 , further comprising:

a source region and a drain region formed on the insulating layer and disposed adjacent first and second ends, respectively, of the fin structure.

4. The memory device of claim 3 , further comprising:

an oxide layer formed on the fin structure, the oxide layer acting as a tunnel oxide layer for the memory device.

5. The memory device of claim 1 , wherein the fin structure has a width ranging from about 100 Å to about 1000 Å.

6. The memory device of claim 1 , wherein the semiconducting layer comprises polycrystalline silicon having a thickness ranging from about 150 Å to about 400 Å.

7. The memory device of claim 1 , wherein the dielectric layer has a thickness ranging from about 200 Å to about 800 Å.

8. The memory device of claim 1 , wherein the control gate comprises polycrystalline silicon having a thickness ranging from about 200 Å to about 1000 Å.

9. A memory device, comprising:

a substrate;

an insulating layer formed on the substrate;

a fin structure formed on the insulating layer, the fin structure comprising a first portion and a second portion formed on the first portion, the first portion comprising a non-strained material and the second portion comprising a strained material;

a floating gate formed above the fin structure;

a dielectric layer formed on the floating gate, the dielectric layer acting as an inter-gate dielectric for the memory device; and

a control gate formed on the dielectric layer.

10. The memory device of claim 9 , wherein the first portion of the fin structure has a thickness greater than the thickness of the second portion of the fin structure.

11. The memory device of claim 9 , further comprising:

a source region and a drain region formed on the insulating layer and disposed adjacent first and second ends, respectively, of the fin structure; and

an oxide layer formed on the fin structure, the oxide layer acting as a tunnel oxide layer for the memory device.

12. The memory device of claim 9 , wherein the fin structure has a width ranging from about 100 Å to about 1000 Å.

13. The memory device of claim 9 , wherein the floating gate comprises polycrystalline silicon having a thickness ranging from about 150 Å to about 400 Å and the dielectric layer has a thickness ranging from about 200 Å to about 800 Å.

14. The memory device of claim 9 , wherein the control gate comprises polycrystalline silicon having a thickness ranging from about 200 Å to about 1000 Å.

15. The memory device of claim 9 , wherein the insulating layer comprises a buried oxide layer and the substrate comprises silicon-germanium.

16. The memory device of claim 9 , wherein the non-strained material comprises silicon-germanium.

17. The memory device of claim 9 , wherein the strained material comprises silicon.

18. The memory device of claim 9 , wherein the non-strained material comprises silicon-germanium and the strained material comprises silicon.

Assignments (10)