Test systems and methods for integrated circuit devices
View Patent ↗One embodiment of the invention is a portion of a test system that includes a timing generation circuit and a formatter that are coupled together, which are on a single CMOS (complementary metal oxide semiconductor) integrated circuit. The timing Generation circuit generates software words. The formatter receives the software words and provides a specified number of transitions per second and a specified edge placement resolution and accuracy. It is noted that the formatter includes a drive circuit and a response circuit. Specifically, the drive circuit includes a plurality of slices, where each slice receives an independent data stream and produces an independent formatted level. The response circuit includes a plurality of slices, where each slice receives an independent data stream and produces an independent strobe marker.
1. A system comprising:
on a single complementary metal oxide semiconductor (CMOS) integrated circuit,
a timing generation circuit operative to provide timing information signals; and
a formatter in communication with the timing generation circuit, the formatter operative to receive timing information signals from the timing generation circuit and to provide a specified number of transitions per second and a specified edge placement resolution and a specified accuracy, wherein the specified accuracy is between approximately 60 ps and approximately 100 ps, wherein the formatter comprises:
a drive circuit, the drive circuit comprising a plurality of slices, each slice operative to receive an independent data stream and to produce an independent formatted level; and
a response circuit, the response circuit comprising a plurality of slices, each slice operative to receive an independent data stream and to produce an independent strobe marker.
2. The system of claim 1 wherein the specified number of transitions per second is between approximately 400 mega transitions per second and approximately 1600 mega transitions per second.
3. The system of claim 1 wherein the specified edge placement resolution is between approximately 10 ps and approximately 30 ps.
4. The system of claim 1 wherein the driver circuit further comprises a global timing measurement unit multiplexer coupled to said plurality of slices of said driver circuit.
5. A system comprising:
on a single complementary metal oxide semiconductor (CMOS) integrated circuit,
a timing generation circuit operative to provide timing information signals; and
a formatter in communication with the timing generation circuit, the formatter operative to receive timing information signals from the timing generation circuit and to provide a specified number of transitions per second and a specified edge placement resolution and a specified accuracy, wherein the specified accuracy is between approximately 60 ps and approximately 100 ps.
6. The system of claim 5 wherein the specified number of transitions per second is between approximately 400 mega transitions per second and approximately 1600 mega transitions per second.
7. The system of claim 5 wherein the specified edge placement resolution is between approximately 10 ps and approximately 30 ps.
8. The system of claim 5 wherein the formatter comprises a response circuit that comprises a plurality of slices, each slice operative to receive an independent data stream and to produce a strobe marker, the response circuit further comprises a global timing measurement unit multiplexer coupled to said plurality of slices of said response circuit.
9. The system of claim 5 wherein the formatter comprises a driver circuit, the drive circuit comprising a plurality of slices, each slice operative to receive an independent data stream and to produce a formatted level.
10. The system of claim 9 wherein each slice comprises:
a plurality of event logic interfaces, each event logic interface capable of decoding signals received from the timing generation circuit;
a plurality of delay line elements, each delay line element been coupled to a corresponding event logic interface and being capable of generating timing markers corresponding to signals received from an event logic interface; and
drive logic coupled to the plurality of delay line elements and operative to produce formatted levels in response to timing markers received from the delay line elements.
11. The system of claim 9 wherein the number of slices is 8.
12. The system of claim 10 wherein the number of event logic interfaces is 4 and the number of delay line elements is 4.
13. The system of claim 5 wherein the formatter comprises a response circuit, the response circuit comprising a plurality of slices, each slice operative to receive an independent data stream and to produce a strobe marker.
14. The system of claim 13 wherein each slice comprises:
a plurality of event logic interfaces, each event logic interface capable of decoding signals received from the timing generation circuit;
a plurality of delay line elements, each delay line element being coupled to a corresponding event logic interface and being capable of generating timing markers corresponding to signals received from an event logic interface; and
response logic coupled to the plurality of delay line elements and operative to produce stroke markers in response to timing markers received from the delay line elements.
15. A method for testing a device under test, the method comprising:
providing a formatter operative to supply a specified number of transitions per second and a specified edge placement resolution and a specified accuracy, wherein the specified accuracy is between approximately 60 ps and approximately 100 ps, the formatter comprising:
a drive circuit, the drive circuit comprising a plurality of slices, each slice operative to receive an independent data stream and to produce a formatted level; and
independently controlling each slice to independently test a plurality of device under test pins.
16. The method of claim 15 wherein providing the formatter comprises:
providing, on a single complementary metal oxide semiconductor (CMOS) integrated circuit, a timing generation circuit and a formatter and wherein the formatter is in communication with the timing generation circuit.
17. The method of claim 15 wherein the specified number of transitions per second is between approximately 400 mega transitions per second and approximately 1600 mega transitions per second.
18. The method of claim 15 wherein the specified edge placement resolution is between approximately 10 ps and approximately 30 ps.
19. The method of claim 15 wherein the driver circuit further comprises a global timing measurement unit multiplexer and a global register section, the global timing measurement unit multiplexer is coupled to said plurality of slices of said driver circuit, and the global register section is coupled to the global timing measurement unit multiplexer.