Valid bit generation and tracking in a pipelined processor
View Patent ↗In an embodiment, a pipelined digital signal processor (DSP) may generate a valid bit in an alignment stage. The valid bit may be qualified in a decode stage in response to receiving a stall signal and/or a kill signal. The valid bit output from the decode stage may be stored in a latch in an address calculation (AC) stage. The valid bit may be held in the latch by a latch enable circuit in response to receiving a stall signal. The valid bit output from the latch may be qualified in the AC stage. The circuit in the AC stage including the latch, the latch enable circuit, and a valid bit qualifier may be repeated in downstream pipeline stages, for example, the execution stages.
1. An apparatus comprising:
a digital signal processor including a pipeline having a plurality of pipeline stages;
a valid bit generator in a first pipeline stage to generate a valid bit;
a signal generator to generate and transmit stall signals and kill signals to a plurality of said pipeline stages;
a first valid bit qualifier in a second pipeline stage to set the valid bit to an invalid value in response to receiving at least one of a stall signal and a kill signal;
a first latch to store the valid bit output from the first valid bit qualifier;
a first latch enable circuit connected to the first latch, said first latch enable circuit adapted to hold the valid bit in the first latch in response to receiving a stall signal; and
a second valid bit qualifier in a third pipeline stage to set the valid bit output from the first latch to an invalid value in response to receiving at least one of a stall signal and a kill signal.
2. The apparatus of claim 1 , further comprising:
a second latch to store the valid bit output from the first valid bit qualifier;
a second latch enable circuit connected to the second latch, said second latch enable circuit adapted to hold the valid bit in the second latch in response to receiving a stall signal; and
a third valid bit qualifier in a fourth pipeline stage to set the valid bit output from the second latch to an invalid value in response to receiving at least one of a stall signal and a kill signal.
3. The apparatus of claim 1 , wherein the valid bit generator comprises a 2-bit instruction width register connected to an OR gate having two inputs.
4. The apparatus of claim 1 , wherein each of the first and second valid bit qualifiers include an AND gate comprising:
an input to receive a valid bit;
a first inverted input to receive a stall signal; and
a second inverted input to receive a kill signal.
5. The apparatus of claim 1 , wherein the latch enable circuit comprises an OR gate having an inverted input to receive a stall signal and an input to receive a kill signal.
6. A method comprising:
generating a valid bit in a first pipeline stage in a pipeline including a plurality of pipeline stages;
transmitting the valid bit to a second pipeline stage;
setting the valid bit to an invalid value in response to receiving at least one of a stall signal and a kill signal in the second pipeline stage;
storing the valid bit in a first latch in one of the second pipeline stage and a third pipeline stage;
holding the valid bit in the first latch in response to receiving a stall signal; and
setting the valid bit output from the first latch to an invalid value in response to receiving at least one of a stall signal and a kill signal in the third pipeline stage.
7. The method of claim 6 , wherein generating the valid bit comprises:
determining a width of an instruction in the first pipeline stage;
setting the valid bit to an invalid value in response to the width having a zero value; and
setting the valid bit to a valid value in response to the width having a non-zero value.
8. The method of claim 6 , further comprising:
storing the valid bit in the third pipeline stage; and
holding the valid bit in the third pipeline stage in response to receiving a stall signal in the third.
9. An article including instructions residing on a machine-readable medium including machine-executable instructions to cause a machine to:
generate a valid bit in a first pipeline stage in a pipeline including a plurality of pipeline stages;
transmit the valid bit to a second pipeline stage;
set the valid bit to an invalid value in response to receiving at least one of a stall signal and a kill signal in the second pipeline stage;
store the valid bit in a first latch in one of the second pipeline stage and a third pipeline stage;
hold the valid bit in the first latch in response to receiving a stall signal; and
set the valid bit output from the first latch to an invalid value in response to receiving at least one of a stall signal and a kill signal in the third pipeline stage.
10. The article of claim 9 , wherein the instructions to cause the machine to generate the valid bit comprise instructions to cause the machine to:
determine a width of an instruction in the first pipeline stage;
set the valid bit to an invalid value in response to the width having a zero value; and
set the valid bit to a valid value in response to the width having a non-zero value.
11. The article of claim 9 , wherein the instructions to cause the machine to generate the valid bit comprise instructions to cause the machine to:
store the valid bit in the third pipeline stage; and
hold the valid bit in the third pipeline stage in response to receiving a stall signal in the third.