IP Library › Assignment 018891/0599
Patent Assignment
Reel/Frame 018891/0599

Assignment of Assignor's Interest

Recorded: 2007-02-09 Pages: 28
Assignor
INTEL CORPORATION
Executed: 2006-11-08
Assignee
ANALOG DEVICES, INC.
ONE TECHNOLOGY WAY, P.O. BOX 9106, NORWOOD, MASSACHUSETTS, 02062-9106
Covered Properties (51)
Multi-Tiered Memory Bank Having Different Data Buffer Sizes with a Programmable Bank Select
Patent: 6,606,684 →
Application: 09/541,114 →
Selectively Processing Different Size Data in Multiplier and Alu Paths in Parallel
Patent: 6,725,360 →
Application: 09/541,116 →
System Having a Configurable Cache/Sram Memory
Patent: 6,446,181 →
Application: 09/541,117 →
Dsp Unit for Multi-Level Global Accumulation
Patent: 6,601,077 →
Application: 09/541,148 →
Adaptive Early Exit Techniques in Image Correlation
Patent: 6,700,996 →
Application: 09/589,624 →
Adaptive Early Exit Techniques in Image Correlation
Patent: 6,654,502 →
Application: 09/589,630 →
Adaptive Early Exit Techniques in Image Correlation
Patent: 6,907,080 →
Application: 09/590,028 →
General Purpose Register File Architecture for Aligned Simd
Patent: 7,120,781 →
Application: 09/608,983 →
Event Vector Table Override
Patent: 6,760,800 →
Application: 09/672,289 →
Maintaining Even and Odd Array Pointers to Extreme Values by Searching and Comparing Multiple Elements Concurrently Where a Pointer Is Adjusted After Processing to Account for a Number of Pipeline Stages
Patent: 6,948,056 →
Application: 09/675,066 →
Fifo Write/Lifo Read Trace Buffer with Software and Hardware Loop Compression
Patent: 7,155,570 →
Application: 09/675,569 →
Valid Bit Generation and Tracking in a Pipelined Processor
Patent: 6,754,808 →
Application: 09/675,712 →
Decode and Dispatch of Multi-Issue and Multiple Width Instructions
Patent: 7,069,420 →
Application: 09/675,815 →
Decoding an Instruction Portion and Forwarding Part of the Portion to a First Destination, Re-Encoding a Different Part of the Portion and Forwarding to a Second Destination
Patent: 6,976,151 →
Application: 09/675,816 →
Aligning Instructions Using a Variable Width Alignment Engine Having an Intelligent Buffer Refill Mechanism
Patent: 7,082,516 →
Application: 09/675,817 →
Instruction Address Generation and Tracking in a Pipelined Processor
Patent: 6,789,184 →
Application: 09/676,058 →
Register Move Operations
Patent: 6,728,870 →
Application: 09/680,894 →
Resetting a Programmable Processor
Patent: 6,665,795 →
Application: 09/684,113 →
Efficient Emulation Instruction Dispatch Based on Instruction Width
Patent: 7,366,876 →
Application: 09/704,467 →
Hardware Loops
Patent: 6,766,444 →
Application: 09/705,070 →
Hardware Loops
Patent: 6,898,693 →
Application: 09/705,088 →
Event Handling
Patent: 6,842,812 →
Application: 09/705,207 →
Hardware Loops
Patent: 6,748,523 →
Application: 09/705,217 →
Processor idle state
Application: 09/711,496 →
Processor Stalling Using a Set of Stall Signals That Are Specific to Stages of a Pipeline
Patent: 7,028,165 →
Application: 09/731,198 →
Publication: US 2002/0069348
Multi-Cycle Instructions
Patent: 7,472,259 →
Application: 09/731,523 →
Publication: US 2002/0103991
Exception Handling Using an Exception Pipeline in a Pipelined Processor
Patent: 6,823,448 →
Application: 09/738,081 →
Publication: US 2002/0078334
Resetting Processor by Provideing a Extended Reset Signal to Disable Instruction Request Logic and Suspend Instruction Fetches
Patent: 6,789,187 →
Application: 09/738,082 →
Publication: US 2002/0078336
Data Synchronization for a Test Access Port
Patent: 7,168,032 →
Application: 09/738,405 →
Publication: US 2002/0078420
Single-Step Processing and Selecting Debugging Modes
Patent: 6,986,026 →
Application: 09/738,649 →
Publication: US 2004/0073780
Watchpoint Engine for a Pipelined Processor
Patent: 6,829,701 →
Application: 09/739,092 →
Publication: US 2002/0078329
Register Adjustment Based on Adjustment Values Determined at Multiple Stages Within a Pipeline of a Processor
Patent: 6,920,547 →
Application: 09/742,745 →
Publication: US 2002/0078326
Hardware Loops and Pipeline System Using Advanced Generation of Loop Parameters
Patent: 7,065,636 →
Application: 09/745,104 →
Publication: US 2002/0078333
Modulo Addressing
Patent: 6,760,830 →
Application: 09/751,507 →
Publication: US 2002/0124039
Security on Hardware Loops
Patent: 6,763,453 →
Application: 09/753,081 →
Publication: US 2002/0087853
Use of a Future File for Data Address Calculations in a Pipelined Processor
Patent: 6,898,695 →
Application: 09/820,514 →
Publication: US 2002/0144089
Method and Apparatus for Restoring Registers After Cancelling a Multi-Cycle Instruction
Patent: 6,889,316 →
Application: 09/820,570 →
Publication: US 2002/0144093
Early Exception Detection
Patent: 6,920,515 →
Application: 09/823,095 →
Publication: US 2002/0144041
Peak Power Reduction When Updating Future File
Patent: 7,124,285 →
Application: 09/823,276 →
Publication: US 2002/0144100
Self-Nesting Interrupts
Patent: 7,043,582 →
Application: 10/236,856 →
Publication: US 2004/0049621
Method and Apparatus for Testing Embedded Cores
Patent: 7,313,739 →
Application: 10/335,149 →
Publication: US 2004/0128596
Dsp Unit for Multi-Level Global Accumulation
Patent: 6,820,102 →
Application: 10/630,517 →
Publication: US 2004/0071041
Multi-Tiered Memory Bank Having Different Data Buffer Sizes with a Programmable Bank Select
Patent: 6,898,690 →
Application: 10/639,020 →
Publication: US 2004/0034739
Adaptive Early Exit Techniques in Image Correlation
Patent: 7,154,950 →
Application: 10/721,593 →
Publication: US 2004/0105496
Adaptive Early Exit Techniques in Image Correlation
Patent: 7,031,498 →
Application: 10/775,261 →
Publication: US 2004/0156532
Dsp Execution Unit for Efficient Alternate Modes for Processing Multiple Data Sizes
Patent: 7,047,271 →
Application: 10/828,913 →
Publication: US 2004/0199558
Valid Bit Generation and Tracking in a Pipelined Processor
Patent: 7,036,000 →
Application: 10/847,837 →
Publication: US 2004/0210744
Early Exception Detection
Patent: 7,272,705 →
Application: 11/135,862 →
Publication: US 2005/0223205
Adaptive Early Exit Techniques in Image Correlation
Patent: 8,804,844 →
Application: 11/138,825 →
Publication: US 2005/0213667
Maintaining even and odd array pointers to extreme values by searching and comparing multiple elements concurrently where a pointer is adjusted after processing to account for a number of pipeline stages
Application: 11/231,397 →
Publication: US 2006/0101230
Variable Width Alignment Engine for Aligning Instructions Based on Transition Between Buffers
Patent: 7,360,059 →
Application: 11/347,097 →
Publication: US 2006/0149928
Related Assignments (25)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest Jun 7, 2000
From: ALDRICH, BRADLEY C.; FRIDMAN, JOSE
To: INTEL CORPORATION; ANALOG DEVICES, INC.
Reel/Frame 010865/0963 →
Assignment of Assignor's Interest Jun 7, 2000
From: ALDRICH, BRADLEY C.; FRIDMAN, JOSE
To: INTEL CORPORATION; ANALOG DEVICES, INC.
Reel/Frame 010849/0063 →
Assignment of Assignor's Interest Jun 7, 2000
From: ALDRICH, BRADLEY C.; FRIDMAN, JOSE
To: INTEL CORPORATION; ANALOG DEVICES, INC.
Reel/Frame 010861/0184 →
Assignment of Assignor's Interest Aug 21, 2000
From: ALDRICH, BRADLEY C.; FRIDMAN, JOSE; MEYER, PAUL
To: INTEL CORPORATION; ANALOG DEVICES, INC.
Reel/Frame 011109/0297 →
Assignment of Assignor's Interest Aug 21, 2000
From: RAMAGOPAL, HEBBALALU S.; WITT, DAVID B.; ALLEN, MICHAEL; SYED, MOINUL
To: INTEL CORPORATION
Reel/Frame 011109/0326 →
Assignment of Assignor's Interest Aug 22, 2000
From: RAMAGOPAL, HEBBALALU S.; ALLEN, MICHAEL; FRIDMAN, JOSE; HOFFMAN, MARC
To: INTEL CORPORATION
Reel/Frame 011108/0124 →
Assignment of Assignor's Interest Aug 22, 2000
From: ALDRICH, BRADLEY C.; KOLAGOTLA, RAVI
To: INTEL CORPORATION
Reel/Frame 011107/0977 →
Assignment of Assignor's Interest Sep 28, 2000
From: ROTH, CHARLES P.; KOLAGOTIA, RAVI; FRIDMAN, JOSE
To: INTEL CORPORATION
Reel/Frame 011217/0076 →
Assignment of Assignor's Interest Sep 28, 2000
From: ROTH, CHARLES P.; KOLAGOTLA, RAVI; FRIDMAN, JOSE
To: INTEL CORPORATION; ANALOG DEVICES, INC.
Reel/Frame 011209/0465 →
Assignment of Assignor's Interest Oct 6, 2000
From: ROTH, CHARLES P.; SINGH, RAVI P.; OVERKAMP, GREGORY A.; INOUE, RYO
To: INTEL CORPORATION
Reel/Frame 011253/0765 →
Assignment of Assignor's Interest Oct 6, 2000
From: ROTH, CHARLES P.; SINGH, RAVI P.; OVERKAMP, GREGORY A.
To: INTEL CORPORATION
Reel/Frame 011227/0285 →
Assignment of Assignor's Interest Oct 31, 2000
From: ROTH, CHARLES P.; SINGH, RAVI P.; OVERKAMP, GREGORY A.; DINH, TIEN
To: INTEL CORPORATION
Reel/Frame 011271/0016 →
Assignment of Assignor's Interest Nov 6, 2000
From: KOLAGOTLA, RAVI; WITT, DAVID B.; ALDRICH, BRADLEY C.
To: INTEL CORPORATION
Reel/Frame 011233/0270 →
Assignment of Assignor's Interest Nov 13, 2000
From: ROTH, CHARLES P.; SINGH, RAVI P.; TOMAZIN, THOMAS; WITT, DAVID B.
To: INTEL CORPORATION
Reel/Frame 011324/0035 →
Assignment of Assignor's Interest Nov 16, 2000
From: ROTH, CHARLES P.; SINGH, RAVI P.; OVERKAMP, GREGORY A.
To: INTEL CORPORATION; ANALOG DEVICES, INC.
Reel/Frame 011296/0190 →
Assignment of Assignor's Interest Dec 6, 2000
From: ROTH, CHARLES P.; SINGH, RAVI P.; OVERKAMP, GREGORY A.
To: INTEL CORPORATION; ANALOG DEVICES, INC.
Reel/Frame 011359/0645 →
Assignment of Assignor's Interest Dec 8, 2000
From: SINGH, RAVI P.; ROTH, CHARLES P.; OVERKAMP, GREGORY A.
To: INTEL CORPORATION; ANALOG DEVICES, INC.
Reel/Frame 011355/0769 →
Assignment of Assignor's Interest Dec 11, 2000
From: SINGH, RAVI P.; ROTH, CHARLES P.; OVERKAMP, GREGORY A.
To: INTEL CORPORATION; ANALOG DEVICES, INC.
Reel/Frame 011375/0734 →
Assignment of Assignor's Interest Dec 11, 2000
From: SINGH, RAVI P.; ROTH, CHARLES P.; OVERKAMP, GREGORY A.
To: INTEL CORPORATION; ANALOG DEVICES, INC.
Reel/Frame 011371/0670 →
Corrective Assignment to Correct the Name of the Assignee, Filed on 08-22-2000 Recorded on Reel 011108 Frame 0124 Assignor Hereby Confirms the Assignment of the Entire Interest. Jan 10, 2001
From: RAMAGOPAL, HEBBALALU S.; ALLEN, MICHAEL; FRIDMAN, JOSE; HOFFMAN, MARC
To: INTEL CORPORATION; ANALOG DEVICES, INC.
Reel/Frame 013736/0036 →
Re-Record to Add the Name of the Second Assignee, Previously Recorded on Reel 011108 Frame 0124, Assignor Confirms the Assignment of the Entire Iinterest. Jan 12, 2001
From: RAMAGOPAL, HEBBALALU S.; ALLEN, MICHAEL; FRIDMAN, JOSE; HOFFMAN, MARC
To: INTEL CORPORATION; ANALOG DEVICES, INC.
Reel/Frame 011440/0499 →
Assignment of Assignor's Interest Jan 12, 2001
From: OVERKAMP, GREGORY A.; ROTH, CHARLES P.; SINGH, RAVI P.
To: INTEL CORPORATION; ANALOG DEVICES, INC.
Reel/Frame 011440/0471 →
Assignment of Assignor's Interest Jan 12, 2001
From: OVERKAMP, GREGORY A.; ROTH, CHARLES P.; SINGH, RAVI P.
To: INTEL CORPORATION; ANALOG DEVICES, INC.
Reel/Frame 011443/0546 →
Assignment of Assignor's Interest Feb 5, 2001
From: INTEL CORPORATION
To: INTEL CORPORATION; ANALOG DEVICES, INC.
Reel/Frame 011502/0157 →
Assignment of Assignor's Interest Feb 5, 2001
From: INTEL CORPORATION
To: INTEL CORPORATION; ANALOG DEVICES INC.
Reel/Frame 011501/0338 →