Method and apparatus for testing embedded cores

1. Apparatus comprising:

a pipelined memory including multiple stages and a plurality of memory elements having addresses;

a test module operative to perform a test on the plurality of memory elements by writing test data to the plurality of memory elements in the pipelined memory, redundantly writing said test data n−1times to the plurality of memory elements, and reading the test data from the plurality of memory elements;

a first storage unit;

a comparator to compare test output data that is output from the pipelined memory with data expected to be output from the pipelined memory to identify a failure of a memory element;

logic to account for a timing latency that arises due to the multiple stages and identify an address of said memory element based on memory addresses of the test data input into the pipelined memory in response to receipt of a notification of the failure from the comparator; and

a fail trace module operative to interrupt the test in response to the identification of the failure of a memory element and to store the identified address of said memory element in the storage unit thereby making the identified address available for output,

where n is the number of pipeline stages.

2. The apparatus of claim 1 , wherein the test comprises a Built-In Self Test (BIST).

3. The apparatus of claim 1 , wherein the memory comprises an embedded memory.

4. The apparatus of claim 1 , wherein the test module is operative to perform the test on the plurality of memory elements in a sequence.

5. The apparatus of claim 1 wherein the fail trace module is further operative to restart the test at a next memory element in the sequence.

6. The apparatus of claim 1 , further comprising a second storage unit, and wherein the fail trace module is further operative to store a data element stored at the memory element at which the test was interrupted in response to identifying the failure.

7. The apparatus of claim 1 , wherein the test module further comprises:

a pattern generator to generate a test pattern;

a finite state machine operative to apply said test pattern to the plurality of memory elements; and

a comparator operative to compare values in the plurality of memory elements with the test pattern.

8. A method comprising:

writing a test pattern to a plurality of memory elements having addresses in a pipelined memory having multiple stages;

reading the plurality of memory elements in a sequence, wherein said reading comprises reading the test data from the plurality of memory elements and redundantly reading the test data n−1 times from the plurality of memory elements;

identifying a fault at one of said memory elements;

accounting for a timing latency that arises due to the multiple stages and identifying an address of said one of said memory elements based on memory addresses of the test pattern and the identifying of the fault;

storing the identified address of said one of said memory elements thereby making the identified address available for output; and

resuming reading the plurality of memory elements at a next memory element in the sequence,

where n is the number of pipeline stages.

9. The method of claim 8 , wherein said identifying comprises:

comparing data read from the plurality of memory elements to the test pattern; and

identifying a miscompare between a data element stored in said one of said memory elements and a corresponding data element in the test pattern.

10. The method of claim 9 , further comprising: storing the data element stored in said one of said memory elements.

11. The method of claim 8 , wherein said writing comprises writing a Built-in Self Test (BIST) test pattern.

12. The method of claim 8 , wherein said storing comprises latching the address into a register.

13. The method of claim 8 , wherein:

storing the identified address comprises storing the identified address in a storage unit of a BIST controller; and the method further comprises

repeating the writing of the test pattern, the reading of the plurality of memory elements, the identifying of a fault, the identifying of an address, the storing of the identified address, and the resuming of the reading until the reading of the plurality of memory elements is completed,

incorporating the identified addresses into a collection of addresses of memory elements, and

outputting the memory element address collection from the BIST controller.

14. The method of claim 13 , wherein incorporating the identified addresses comprises incorporating the identified addresses into a bitmap.

15. A method of testing a pipelined memory, comprising:

writing test data to a plurality of memory elements in the pipeliried memory;

redundantly writing said test data n−1 times to the plurality of memory elements;

reading the test data from the plurality of memory elements;

identifying an address of a failing memory element based on at least some of the read test data; and

making the address of a failing memory element available for output,

where n is the number of pipeline stages.

16. The method of claim 15 , further comprising:

redundantly writing test data for a plurality of read cycles.

17. The method of claim 15 , wherein said writing the test data comprises writing a Built-in Self Test (BIST) test pattern.

18. A method of testing a pipelined memory, comprising:

writing test data to a plurality of memory elements in the pipelined memory;

reading the test data from the plurality of memory elements; and

redundantly reading the test data n−1 times from the plurality of memory elements;

identifying an address of a failing memory element based on at least some of the read test data; and

making the address of a failing memory element available for output,

where n is the number of pipeline stages.

19. The method of claim 18 , further comprising:

redundantly reading test data for a plurality of read cycles.

20. The method of claim 18 , wherein said writing the test data comprises writing a Built-in Self Test (BIST) test pattern.