Vertically stacked, field programmable, nonvolatile memory and method of fabrication
View Patent ↗A three-dimensional, field-programmable, non-volatile memory includes multiple layers of first and second crossing conductors. Pillars are self-aligned at the intersection of adjacent first and second crossing conductors, and each pillar includes at least an anti-fuse layer. The pillars form memory cells with the adjacent conductors, and each memory cell includes first and second diode components separated by the anti-fuse layer. The diode components form a diode only after the anti-fuse layer is disrupted.
1. A process for fabricating a state change element in a semiconductor memory device comprising the steps of:
forming a first semiconductor layer,
forming a grown anti-fuse layer overlying and in contact with the first semiconductor layer without first planarizing the first semiconductor layer; and
forming a second semiconductor layer on and in contact with the anti-fuse layer, wherein
said memory device comprises first and second diode components separated by the anti-fuse layer, said diode components forming a diode only after the anti-fuse layer is disrupted, and wherein the first diode component, the grown anti-fuse layer, and the second diode component are in the form of a pillar.
2. The process of claim 1 , wherein the step of forming a grown anti-fuse layer comprises growing silicon dioxide.
3. The process of claim 1 , wherein the step of forming a grown anti-fuse layer comprises growing silicon nitride.
4. The process of claim 1 , wherein the step of forming a first semiconductor layer comprises forming a first layer of polycrystalline silicon doped with a conductivity determining dopant.
5. The process of claim 1 , wherein the step of forming a first semiconductor layer comprises forming a layer of amorphous silicon.
6. The process of claim 1 , wherein the step of forming a first semiconductor layer comprises forming a layer of recrystallized silicon.
7. A process for fabricating a memory cell comprising:
forming two diode components; and
forming an anti-fuse layer between the diode components,
wherein the anti-fuse layer is formed by an oxidation of a surface of a semiconductor material of the one of the diode components without planarization of the surface.
8. The process of claim 7 , wherein the oxidation forms a silicon dioxide layer on the semiconductor material within the one of the diode components.
9. A process for fabricating a cell in a 3-D, field-programmable, non-volatile memory comprising:
forming a first conductor layer;
forming a semiconductor layer overlying the conductor layer;
oxidizing at least a portion of the semiconductor layer to form an oxide layer thereon without first planarizing the semiconductor layer;
forming a silicon layer overlying the oxide layer;
sequentially etching the silicon layer, the oxide layer, and the semiconductor layer to form a pillar of the cell, and
forming a second conductor layer overlying the second semiconductor layer; wherein
said cell comprises first and second diode components separated by the oxide layer, said diode components forming a diode only after the oxide layer is disrupted.
10. The process of claim 9 , wherein the first conductor layer comprises a refractory metal.
11. The process of claim 10 , wherein the refractory metal is tungsten.
12. The process of claim 9 wherein the silicon layer overlying the oxide layer comprises a lightly-doped silicon layer and a heavily doped silicon layer.
13. The process of claim 9 wherein the semiconductor layer overlaying the conductor layer comprises a lightly-doped silicon layer and a heavily doped silicon layer.