Semiconductor devices and fabrication methods thereof
View Patent ↗Semiconductor devices and methods of fabricating semiconductor devices are disclosed. A disclosed semiconductor device includes a silicon substrate, a source region and a drain region. A gate electrode is formed on the silicon substrate. Also, a metal silicide layer is formed on each of the gate electrode, the source region, and the drain region. The metal silicide layer has a thickness uniformity of about 1˜20%. A disclosed fabrication method includes forming a metal layer on a silicon substrate having a gate electrode, a source region, and a drain region; performing a plasma treatment on the metal layer; forming a protective layer on the metal layer; and heat treating the silicon substrate on which the protective layer is formed to thereby form a metal silicide layer. A gas that includes nitrogen is used as a plasma gas during the plasma treatment.
1. A method of fabricating a semiconductor device, comprising:
forming a metal layer on a silicon substrate having a gate electrode, a source region, and a drain region;
performing a plasma treatment with a gas comprising nitrogen on the metal layer, wherein nitrogen is added to metal layer;
forming a protective layer on the metal layer; and
heat treating the silicon substrate having the protective layer to thereby form a metal silicide layer containing nitrogen and having a thickness of about 100˜400 Å and a thickness uniformity of about 1˜20%.
2. A method as defined in claim 1 , wherein to gas comprising nitrogen comprises one of N 2 gas and NH3 gas.
3. A method as defined in claim 1 , wherein forming the metal layer comprises depositing a nickel layer.
4. A method as defined in claim 3 , wherein depositing a nickel layer comprises a PVD process or a CVD process.
5. A method us defined in claim 1 , wherein the plasma treatment is performed in-situ in a same chamber used to form the metal layer.
6. A method as defined in claim 1 , wherein the nitrogen, which reduces a speed at which the metal silicide layer grows, is injected into the metal layer trough the plasma treatment.
7. A method as defined in claim 1 , wherein forming the metal layer, performing the plasma treatment, forming the protective layer, and heat treating the silicon substrate are all performed in a same chamber.
8. A method as defined in claim 1 , wherein forming the protective layer comprises depositing titanium, titanium nitride, or titanium/titanium nitride.
9. A method as defined in claim 8 , wherein forming the protective layer comprises physical vapor deposition (PVD) or chemical vapor deposition (CVD).
10. A method as defined in claim 1 , wherein heat treating the silicon substrate comprises a first RTP method or heating in an electric furnace.
11. A method as defined in claim 1 , further comprising removing the protective layer and an unreacted portion of the metal layer following the formation of the metal silicide layer.
12. A method as defined in claim 11 , further comprising a second beat treating process following removing the protective layer and the unreacted portion of the metal layer.
13. A method as defined in claim 12 , wherein in the second heat treating process comprises a second RTP method or beating in the electric furnace.
14. A method as defined in claim 1 , wherein the metal silicide layer enters a surface of the silicon substrate to a depth of less than about 400 Å.
15. A method as defined in claim 10 , wherein the first RTP method comprises exposure to a temperature of about 300-600° C. for about 10-60 seconds.
16. A method as defined in claim 10 , wherein heating in an the electric furnace comprises exposure to a temperature of about 300-600° C. for about 20-60 seconds.
17. A method as defined in claim 13 , wherein the second RTP method comprises exposure to a temperature of about 900-950° C. for about 10-60 seconds.
18. A method as defined in claim 13 , wherein heating in the electric furnace comprises exposure to a temperature of about 500-900° C. for about 20-60 seconds.
19. A method as defined in claim 1 , further comprising forming nitride spacers on sidewalls of the gate electrode prior to forming the metal layer.