Method for making high density nonvolatile memory
View Patent ↗An improved method for fabricating a three dimensional monolithic memory with increased density. The method includes forming conductors preferably comprising tungsten, then filling and planarizing; above the conductors forming semiconductor elements preferably comprising two diode portions and an antifuse, then filling and planarizing; and continuing to form conductors and semiconductor elements in multiple stories of memories. The arrangement of processing steps and the choice of materials decreases aspect ratio of each memory cell, improving the reliability of gap fill and preventing etch undercut.
1. A three-dimensional memory cell of a first story of an electronic device, the memory cell comprising:
a) a first conductor extending in a first direction;
b) a first semiconductor element over the first conductor, the first semiconductor element comprising:
i) a first heavily doped semiconductor layer of a first conductivity type;
ii) a second heavily doped semiconductor layer of a second conductivity type, the second semiconductor layer disposed above the first semiconductor layer;
iii) a third lightly doped semiconductor layer interposed between the first and second semiconductor layers;
iv) an antifuse layer disposed above the second semiconductor layer or below the first semiconductor layer; and
c) a second conductor over the first conductor, the second conductor extending in a second direction different from the first direction,
wherein the first, second, and third semiconductor layers are not patterned in the same patterning step with the first conductor.
2. The memory cell of claim 1 wherein the antifuse layer is disposed above the second semiconductor layer.
3. The memory cell of claim 2 wherein the antifuse layer is a dielectric layer.
4. The memory cell off claim 3 wherein the antifuse layer comprises silicon dioxide.
5. The memory cell of claim 2 wherein the conductors comprise tungsten.
6. The memory cell of claim 2 wherein the cell is disposed above and not in contact with a monocrystalline semiconductor substrate.
7. The memory cell of claim 1 further comprising a second semiconductor element over the second conductor.
8. The memory cell of claim 7 further comprising a third conductor formed over the second semiconductor element.
9. The memory cell of claim 1 wherein the first semiconductor element comprises polysilicon.
10. The memory cell of claim 1 wherein the first semiconductor element comprises germanium.
11. The memory cell of claim 1 wherein the first semiconductor element comprises silicon-germanium.
12. The memory cell of claim 1 wherein the first semiconductor element comprises silicon-gernanium-carbon.
13. The memory cell of claim 1 wherein the mernory cell is a portion of a monolithic three dimensional memory array.
14. A monolithic three dimensional memory array comprising:
a) a first story of cells, the first story comprising:
i) a first conductor extending in a first direction;
ii) a first semiconductor element comprising a dielectric antifuse layer formed above the first conductor;
iii) a second rail-shaped conductor formed above the first semiconductor element, wherein the dielectric antifuse layer is in contact with the second rail-shaped conductor; and
b) at least a second story of cells formed above the first story,
wherein the first semiconductor element is not patterned in the same patterning step with the first conductor.
15. The memory array of claim 14 wherein the antifuse layer is a dielectric layer.
16. The memory array of claim 15 wherein the antifuse layer is a silicon dioxide layer.
17. The memory array of claim 14 wherein the semiconductor element comprises a first heavily doped semiconductor layer. and wherein the antifuse layer is formed on and in contact with the first heavily doped semiconductor layer.
18. The memory array of claim 14 ,wherein the conductors comprise tungsten.
19. The memory array of claim 14 wherein the first semiconductor element comprises germnanium.
20. The memory array of claim 14 wherein the first semiconductor element comprises silicon-germanium.
21. The memory array of claim 14 wherein the first semiconductor element comprises silicon-germaninum-carbon.
22. The memory army of claim 14 wherein the second conductors of the first story of cells serve as lower conductors of an overlying, second story of cells.
23. A three-dimensional memory cell of a first story of an electronic device, the memory cell comprising:
a) a first conductor extending in a first direction;
b) a first semiconductor element over the first conductor, the first semiconductor element comprising:
i) a fist heavily doped semiconductor layer of a first conductivity type;
ii) a second heavily doped semiconductor layer of a second conductivity type, the second semiconductor layer disposed above the first semiconductor layer;
iii) a third lightly doped semiconductor layer interposed between the first and second semiconductor layers;
iv) an antifuse layer disposed above the second semiconductor layer or below the first semiconductor layer; and
c) a second conductor over the first conductor, the second conductor extending in a second direction different from the first direction,
wherein the first semiconductor element has a substantially cylindrical shape.
24. A monolithic three dimensional memory array comprising:
a) a first story of cells, the first story comprising:
i) a first conductor extending in a first direction;
ii) a first semiconductor element comprising a dielectric antifuse layer formed above the first conductor;
iii) a second rail-shaped conductor formed above the first semiconductor erein the dielectric antifuse layer is in contact with the rail-shaped second conductor; and
b) at least a second story of cells formed above the first story,
wherein the first semiconductor element has a substantially cylindrical shape.