Semiconductor device and method of fabricating the same
View Patent ↗The present invention relates to a semiconductor device and a method of fabricating the same for simplifying a fabrication process of the semiconductor device and enhancing the performance and yield of the device. A first metal wiring on a semiconductor substrate serves as a first electrode of a metal-insulator-metal (MIM) capacitor. A dielectric film pattern is formed on the first metal wiring. A first via-contact plug on the dielectric film pattern contacts a side of the first metal wiring. An interlayer insulation film is formed having second via-contact plugs in a parallel array structure. The second via-contact plugs contact the dielectric film pattern and serve as a second electrode of the MIM capacitor. A second metal wiring is formed on the interlayer insulation film to contact the first via-contact plug and the second via-contact plugs.
1. A method of fabricating a semiconductor device, comprising:
forming a first metal wiring on a semiconductor substrate and a dielectric film pattern on the first metal wiring, the first metal wiring serving as a first electrode of a metal-insulator-metal (MIM) capacitor;
forming a stacked structure comprising a first interlayer insulation film and a second interlayer insulation film;
forming a photosensitive film pattern defining a first via-contact region and a plurality of second via-contact regions on the stacked structure, wherein the photosensitive film pattern exposes the first via-contact region at a first side of the first metal wiring, defines the plurality of second via-contact regions in a parallel array structure at a second side of the first metal wiring, and defines a width of each of the plurality of second via-contact regions smaller than a width of the first via-contact region;
etching the first and second interlayer insulation films and the dielectric film pattern on the first metal wiring using the photosensitive film pattern as an etching mask to form a first via-contact hole exposing the first metal wiring and to form a plurality of second via-contact holes exposing the dielectric film pattern;
removing the photosensitive film pattern;
filling the first second via-contact hole and the plurality of second via-contact holes to form a first contact-plug and a plurality of second via-contact plugs, the plurality of second via-contact plugs serving as a second electrode of the MIM capacitor; and
forming a second metal wiring contacting the first via-contact plug and the plurality of second via-contact plugs.
2. The method in accordance with claim 1 , wherein the first dielectric film pattern comprises a SiO x N y layer, and the second dielectric film pattern comprises an Si 3 N 4 layer.
3. The method in accordance with claim 1 , wherein the etching step comprises at least two etching stages using plasma activated from a C x F y gas.
4. The method in accordance with claim 3 , wherein a first stage of the etching step comprises exposing the first dielectric film pattern in the first via-contact region.
5. The method in accordance with claim 3 , wherein a second stage of the etching step comprises etching the first dielectric film pattern on the first via-contact region by raising a C/F ratio or a C/O ratio in a plasma higher than that of the first stage, and using the second dielectric film pattern as an etch-stop layer to form the first via-contact hole, form the plurality of second via-contact holes, and expose the second dielectric film pattern on the plurality of second via-contact regions.
6. The method in accordance with claim 1 , wherein each of the first via-contact plug and the plurality of second via-contact plugs comprise tungsten.