Granted Patent B1

US 7,053,446 · App. 10/864,142 · Granted May 30, 2006

Abstract

Claims (28)

1. An integrated circuit comprising:

a semiconductor substrate;

a charge-trapping dielectric layer over the semiconductor substrate;

first and second bitlines in the semiconductor substrate;

a doped wordline over the charge-trapping dielectric layer; and

a doped wordline spacer adjacent to the wordline.

2. The integrated circuit as claimed in claim 1 wherein the wordline layer is a doped polysilicon.

3. The integrated circuit as claimed in claim 1 wherein the doped wordline spacer layer is a doped polysilicon.

4. The integrated circuit as claimed in claim 1 additionally comprising:

a silicide on the doped wordline.

5. The integrated circuit as claimed in claim 1 wherein the charge-trapping dielectric layer is composed of:

a first dielectric layer;

a charge-trapping layer over the first dielectric layer; and

a second dielectric layer over the charge-trapping layer.

6. An integrated circuit comprising:

a silicon substrate;

a charge-trapping dielectric layer over the silicon substrate;

first and second bitlines in the silicon substrate;

a doped wordline over the charge-trapping dielectric layer; and

a doped wordline spacer adjacent to and around the doped wordline.

7. The integrated circuit as claimed in claim 6 wherein the wordline layer is a doped polysilicon.

8. The integrated circuit as claimed in claim 6 wherein the doped wordline spacer layer is a doped polysilicon.

9. The integrated circuit as claimed in claim 6 additionally comprising:

a self-align silicide on top of the doped wordline of cobalt, titanium, or nickel silicide.

10. The integrated circuit as claimed in claim 6 wherein the charge-trapping dielectric layer is composed of:

a first oxide layer;

a nitride layer over the first oxide layer; and

a second oxide layer over the nitride layer.

Assignments (7)