Semiconductor package having improved adhesiveness and ground bonding
View Patent ↗A semiconductor package having improved adhesiveness between the chip paddle and the package body and having improved ground-bonding of the chip paddle. A plurality of through-holes are formed in the chip paddle for increasing the bonding strength of encapsulation material in the package body. A plurality of tabs are formed in the chip paddle may also be used alone or in conjunction with the through-holes to further increase the bonding strength of the encapsulation material in the package body. The tabs provide additional area for the bonding site to ground wires from the semiconductor chip by increasing the length of the chip paddle.
1. A semiconductor package, comprising:
a chip paddle having opposed top and bottom paddle surfaces;
a ground ring defined by a peripheral portion of the chip paddle, the ground ring defining opposed top and bottom ring surfaces;
a semiconductor chip attached to the top surface of the chip paddle;
a plurality of leads having opposed top and bottom lead surfaces and extending at least partially about the chip paddle in spaced relation thereto, the ground ring being positioned between the semiconductor chip and the leads, with the semiconductor chip being electrically connected to at least one of the leads; and
an encapsulation material covering the chip paddle, the ground ring, the semiconductor chip and the leads such that at least portions of the bottom lead surfaces of the leads are exposed therein.
2. The semiconductor package of claim 1 wherein the ground ring is partially defined by a plurality of through holes disposed within the chip paddle in spaced relation to earth other.
3. The semiconductor package of claim 2 wherein each of the through holes has an elongate, slot-like configuration.
4. The semiconductor package of claim 1 wherein the chip paddle includes a peripheral half-etched section which circumvents and is recessed relative to the bottom paddle surface, the ground ring being included in the half etched section of the chip paddle.
5. The semiconductor package of claim 4 wherein the ground ring is partially defined by a plurality of trough holes disposed within the half-etched section of the chip paddle.
6. The semiconductor package of claim 1 wherein the top ring surface and the top paddle surface extend in generally co-planar relation to each other.
7. The semiconductor package of claim 6 wherein the top ring surface and the top lead surfaces of the leads extend in generally co-planar relation to each other.
8. The semiconductor package of claim 1 wherein the bottom paddle surface of the chip paddle is exposed in the encapsulation material.
9. The semiconductor package of claim 8 wherein the bottom paddle surface of the chip paddle and the bottom lead surfaces of the leads extend in generally co-planar relation to each other.
10. The semiconductor package of claim 1 wherein the semiconductor chip is electrically connected to the ground ring.
11. The semiconductor package of claim 10 wherein the electrical connection of the semiconductor chip to the ground ring and to at least one of the leads is facilitated by conductive wires which are covered by the encapsulation material.