Patent Assignment
Reel/Frame 054067/0135
Assignment of Assignor's Interest
Recorded: 2020-10-09
Pages: 57
Assignor
AMKOR TECHNOLOGY, INC.
Executed: 2019-11-19
Assignee
AMKOR TECHNOLOGY SINGAPORE HOLDING PTE.LTD.
491 B RIVER VALLEY ROAD, #15-02/04, VALLEY POINT, 248373, SINGAPORE
Covered Properties
(541)
Wafer-Scale Production of Chip-Scale Semiconductor Packages Using Wafer Mapping Techniques
Patent:
6,589,801 →
Application:
09/385,694 →
Method of Making an Integrated Circuit Package Using a Batch Step for Curing a Die Attachment Film and a Tool System for Performing the Method
Patent:
6,517,656 →
Application:
09/412,889 →
Integrated Circuit Device Packages and Substrates for Making the Packages
Patent:
6,580,159 →
Application:
09/434,589 →
Semiconductor Package with Exposed Die Pad and Body-Locking Leadframe
Patent:
6,847,103 →
Application:
09/436,158 →
Thin Image Sensor Package Having Transparent Substrate
Patent:
6,627,864 →
Application:
09/447,202 →
Method of Assembling a Snap Lid Image Sensor Package
Patent:
6,526,653 →
Application:
09/457,515 →
Protected Image Sensor Package
Patent:
6,515,269 →
Application:
09/490,717 →
Protected Image Sensor Package Fabrication Method
Patent:
6,512,219 →
Application:
09/491,112 →
Fabricating Very Thin Chip Size Semiconductor Packages
Patent:
6,656,765 →
Application:
09/496,991 →
Nonexposed Heat Sink for Semiconductor Package
Patent:
7,009,283 →
Application:
09/513,067 →
Method and Apparatus for Increasing Thickness of Molded Body Semiconductor Package
Patent:
6,596,212 →
Application:
09/528,884 →
Flip Chip Image Sensor Package Fabrication Methpd
Patent:
6,571,466 →
Application:
09/536,830 →
Matrix Type Printed Circuit Board for Semiconductor Packages
Patent:
6,580,620 →
Application:
09/548,705 →
Method of Making an Electromagnetic Interference Shield Device
Patent:
6,601,293 →
Application:
09/551,416 →
Semiconductor Package and Method for Fabricating the Same
Patent:
6,515,356 →
Application:
09/566,069 →
Stackable Package Having a Cavity and a Lid for an Electronic Device
Patent:
6,518,659 →
Application:
09/566,658 →
Multi-Stacked Memory Package
Patent:
6,683,377 →
Application:
09/583,183 →
Semiconductor Package with Spacer Strips
Patent:
6,531,784 →
Application:
09/585,915 →
Packaging High Power Integrated Circuit Devices
Patent:
6,521,982 →
Application:
09/587,136 →
Circuit Board Semiconductor Package
Patent:
6,512,288 →
Application:
09/589,713 →
Material Transport Method
Patent:
6,889,813 →
Application:
09/602,162 →
Assembly for Transporting Material
Patent:
6,695,120 →
Application:
09/602,195 →
Gripper Assembly
Patent:
6,530,735 →
Application:
09/602,196 →
Flip-Chip Micromachine Package
Patent:
6,534,876 →
Application:
09/608,298 →
Flip Chip Integrated Circuit and Passive Chip Component Package Fabrication Method
Patent:
6,546,620 →
Application:
09/608,357 →
Stackable Package Having Clips for Fastening Package and Tool for Opening Clips
Patent:
6,667,544 →
Application:
09/608,419 →
Wafer Scale Image Sensor Package Fabrication Method
Patent:
6,503,780 →
Application:
09/610,309 →
Microcircuit Die-Sawing Protector
Patent:
6,563,204 →
Application:
09/615,670 →
Semiconductor Package and Method for Fabricating the Same
Patent:
6,798,049 →
Application:
09/648,284 →
Chip Size Semiconductor Packages with Stacked Dies
Patent:
6,577,013 →
Application:
09/655,439 →
Semiconductor Memory Cards and Method of Making Same
Patent:
6,624,005 →
Application:
09/656,253 →
Multiple Die Lead Frame Package with Enhanced Die-to Die Interconnect Routing Using Internal Lead Trace Wiring
Patent:
6,552,416 →
Application:
09/659,017 →
Micromachine Stacked Wirebonded Package
Patent:
6,522,015 →
Application:
09/670,499 →
Micromachine Stacked Wirebonded Package Fabrication Method
Patent:
6,638,789 →
Application:
09/670,500 →
Micromachine Stacked Flip Chip Package Fabrication Method
Patent:
6,530,515 →
Application:
09/670,501 →
Leadframe and Semiconductor Package with Improved Solder Joint Strength
Patent:
7,102,208 →
Application:
09/687,048 →
Semiconductor Device Having Increased Moisture Path and Increased Solder Joint Strength
Patent:
6,525,406 →
Application:
09/687,049 →
Apparatus for Manufacturing Semiconductor Packages
Patent:
6,616,436 →
Application:
09/687,126 →
Leadframe for Semiconductor Package and Mold for Molding the Same
Patent:
6,627,976 →
Application:
09/687,331 →
Clamp and Heat Block Assembly for Wire Bonding a Semiconductor Package Assembly
Patent:
6,677,662 →
Application:
09/687,487 →
Semiconductor Package Having Improved Adhesiveness and Ground Bonding
Patent:
6,853,059 →
Application:
09/687,493 →
Encapsulated Semiconductor Package Including Chip Paddle and Leads
Patent:
6,753,597 →
Application:
09/687,495 →
Stackable Semiconductor Package and Method for Manufacturing Same
Patent:
6,730,544 →
Application:
09/687,530 →
Stackable Semiconductor Package and Method for Manufacturing Same
Patent:
6,605,866 →
Application:
09/687,531 →
End Grid Array Semiconductor Package
Patent:
6,677,663 →
Application:
09/687,536 →
Semiconductor Package Leadframe Assembly and Method of Manufacture
Patent:
6,555,899 →
Application:
09/687,541 →
Semiconductor Package Having Reduced Thickness
Patent:
6,696,747 →
Application:
09/687,585 →
Thin and Heat Radiant Semiconductor Package and Method for Manufacturing
Patent:
6,646,339 →
Application:
09/687,787 →
Near Chip Size Semiconductor Package
Patent:
6,639,308 →
Application:
09/687,876 →
Plastic Integrated Circuit Device Package and Method for Making the Package
Patent:
6,521,987 →
Application:
09/703,195 →
Chip Size Image Sensor in Wirebond Package with Step-Up Ring for Electrical Contact
Patent:
6,509,560 →
Application:
09/711,993 →
Chip Size Image Sensor Bumper Package Fabrication Method
Patent:
6,629,633 →
Application:
09/711,994 →
Chip Size Image Sensor Bumped Package
Patent:
6,528,857 →
Application:
09/712,313 →
Chip Size Image Sensor Wirebond Package Fabrication Method
Patent:
6,620,646 →
Application:
09/712,314 →
Flip Chip on Glass Image Sensor Package
Patent:
6,849,916 →
Application:
09/713,848 →
Angulated Semiconductor Packages
Patent:
6,532,157 →
Application:
09/714,622 →
Exposed Copper Strap in a Semiconductor Package
Patent:
6,566,164 →
Application:
09/733,148 →
Wire Bonding Method and Semiconductor Package Manufactured Using the Same
Structure of Heat Slug-Equipped Packages and the Packaging Method of the Same
Optical Fiber Having Tapered End and Optical Connector with Reciprocal Opening
Patent:
6,672,773 →
Application:
09/751,536 →
Tool and Method for Forming an Integrated Optical Circuit
Method of Making and Stacking a Semiconductor Package
Patent:
6,564,454 →
Application:
09/752,244 →
Pattern Recognition Method
Clamp for Pattern Recognition
Optical Module with Lens Integral Holder
Patent:
6,686,588 →
Application:
09/764,165 →
Method for Fabricating a Special-Purpose Die Using a Polymerizable Tape
Patent:
6,610,167 →
Application:
09/764,166 →
Structure for Fabricating a Special-Purpose Die Using a Polymerizable Tape
Patent:
6,572,944 →
Application:
09/764,190 →
Optical Module with Lens Integral Holder Fabrication Method
Patent:
7,059,040 →
Application:
09/764,196 →
Semiconductor Package Having Semiconductor Chip Within Central Aperture of Substrate
Back-Side Wafer Singulation Method
Patent:
6,869,861 →
Application:
09/803,083 →
Wafer having alignment marks extending from a first to a second surface of the wafer
Patent:
6,943,429 →
Application:
09/803,084 →
Micromirror Device Package Fabrication Method
Patent:
6,624,921 →
Application:
09/804,805 →
Structure for Protecting a Micromachine with a Cavity in a Uv Tape
Patent:
6,580,153 →
Application:
09/811,183 →
Mounting for a Package Containing a Chip
Patent:
6,545,345 →
Application:
09/813,485 →
Semiconductor Package Including Stacked Chips with Aligned Input/Output Pads
Semiconductor Package
Thermally Enhanced Chip Scale Lead on Chip Semiconductor Package
Patent:
6,597,059 →
Application:
09/825,785 →
Semiconductor Package with Molded Substrate and Recessed Input/Output Terminals
Patent:
6,528,869 →
Application:
09/827,619 →
Making Two Lead Surface Mounting High Power Microleadframe Semiconductor Packages
Patent:
6,756,658 →
Application:
09/827,791 →
Making Leadframe Semiconductor Packages with Stacked Dies and Interconnecting Interposer
Patent:
6,603,072 →
Application:
09/828,046 →
Stackable Lead Frame Package Using Exposed Internal Lead Traces
Patent:
6,791,166 →
Application:
09/829,341 →
Heat Spreader with Spring Ic Package
Patent:
6,580,167 →
Application:
09/839,284 →
Heat Spreader with Spring Ic Package Fabrication Method
Patent:
6,562,655 →
Application:
09/839,288 →
Vacuum Sealed Package for Semiconductor Chip
Patent:
6,528,875 →
Application:
09/839,305 →
Leadframe and Semiconductor Package Made Using the Leadframe
Shielded Semiconductor Leadframe Package
Patent:
6,614,102 →
Application:
09/848,864 →
Shielded Semiconductor Package with Single-Sided Substrate and Method for Making the Same
Patent:
6,707,168 →
Application:
09/848,932 →
Sheet Resin Composition
Multi-Chip Semiconductor Package with Integral Shield and Antenna
Patent:
6,686,649 →
Application:
09/855,244 →
Plastic Integrated Circuit Device Package Having Exposed Lead Surface
Image Sensing Component Package and Manufacture Method Thereof
Personalized Circuit Module Package and Method for Packaging Circuit Modules
Hermetic Ceramic Semiconductor Package
Patent:
6,627,987 →
Application:
09/881,343 →
Integrated Circuit Package Having Posts for Connection to Other Packages and Substrates
Patent:
6,586,826 →
Application:
09/881,344 →
Imprinted Integrated Circuit Substrate and Method for Imprinting an Integrated Circuit Substrate
Patent:
6,967,124 →
Application:
09/884,193 →
Method of Making a Chip Carrier Package Using Laser Ablation
Patent:
6,660,559 →
Application:
09/888,950 →
Optical Track Drain Package
Patent:
6,765,801 →
Application:
09/891,678 →
Method for Molding Semiconductor Package Having a Ceramic Substrate
Patent:
6,534,338 →
Application:
09/895,767 →
Pre-Drilled Image Sensor Package
Patent:
6,548,759 →
Application:
09/895,994 →
Structure for Backside Saw Cavity Protection
Patent:
6,661,080 →
Application:
09/895,996 →
Method for Forming an Image Sensor Package with Vision Die in Lens Housing
Patent:
6,734,419 →
Application:
09/896,014 →
Pre-Drilled Image Sensor Package Fabrication Method
Patent:
6,730,536 →
Application:
09/896,074 →
Method of Fabricating and Using an Image Sensor Package with Reflector
Patent:
6,717,126 →
Application:
09/906,868 →
Image Sensor Package with Reflector
Patent:
6,686,580 →
Application:
09/906,992 →
Integrated Circuit Chip Package Having an Internal Lead
Patent:
6,657,298 →
Application:
09/909,160 →
Reduced Thickness Packaged Electronic Device
Patent:
6,586,824 →
Application:
09/916,716 →
Embedded Heat Spreader Ball Grid Array
Patent:
7,126,218 →
Application:
09/923,834 →
Laser Defined Pads for Flip Chip on Leadframe Package Fabrication Method
Patent:
6,593,545 →
Application:
09/929,428 →
Solderable Injection-Molded Integrated Circuit Substrate and Method Therefor
Patent:
6,784,376 →
Application:
09/931,144 →
Semiconductor Package and Leadframe with Horizontal Leads Spaced in the Vertical Direction and Method of Making
Patent:
7,102,216 →
Application:
09/932,290 →
Semiconductor Package Having Substrate with Laser-Formed Aperture Through Solder Mask Layer
Patent:
6,534,391 →
Application:
09/932,528 →
Method and Circuit Module Package for Automated Switch Actuator Insertion
Vcsel Package and Fabrication Method
Patent:
6,816,523 →
Application:
09/940,103 →
Placement Template and Method for Placing Optical Dies
Patent:
6,861,720 →
Application:
09/943,068 →
Quick Sealing Glass-Lidded Package
Patent:
6,603,183 →
Application:
09/946,750 →
Quick Sealing Glass-Lidded Package Fabrication Method
Patent:
6,759,266 →
Application:
09/946,861 →
Lead-Frame Method and Assembly for Interconnecting Circuits Within a Circuit Module
Patent:
6,900,527 →
Application:
09/956,190 →
Methods of Forming Metallurgy Structures for Wire and Solder Bonding
Semiconductor Package Having Stacked Semiconductor Chips and Method of Making the Same
Patent:
6,555,917 →
Application:
09/974,541 →
Semiconductor Package with Singulation Crease
Apparatus and Method for Allowing Testing of Semiconductor Devices at Different Temperatures
Patent:
6,608,497 →
Application:
09/978,535 →
Multi-Layer Lead Frame Structure
Patent:
6,686,651 →
Application:
09/996,226 →
Semiconductor Package with Optimized Leadframe Bonding Strength
Printed Circuit Board with Integral Heat Sink for Semiconductor Package
Method of Making an Integrated Circuit Package
Power Semiconductor Package with Strap
Patent:
6,630,726 →
Application:
10/008,048 →
Methods of Positioning Components Using Liquid Prime Movers and Related Structures
Sensor Module with Integrated Discrete Components
Patent:
6,630,661 →
Application:
10/012,378 →
Lead Frame for Semiconductor Package
Structures for Improving Heat Dissipation in Stacked Semiconductor Packages
Patent:
6,737,750 →
Application:
10/013,396 →
Methods and Systems for Positioning Substrates Using Spring Force of Phase-Changeable Bumps Therebetween
Low Temperature Methods of Bonding Components and Related Structures
Semiconductor Package Including Flip Chip
Reduced Size Semiconductor Package with Stacked Dies
Electroplating Methods Including Maintaining a Determined Electroplating Voltage and Related Systems
Optical Device Packages Having Improved Conductor Efficiency, Optical Coupling and Thermal Transfer
Semiconductor Package Including Rings Structure Connected to Leads with Vertically Downset Inner Ends
Patent:
6,798,046 →
Application:
10/054,124 →
Thin Integrated Circuit Package Having an Optically Transparent Window
Patent:
6,784,534 →
Application:
10/067,068 →
Integrated Circuit Package Mounting
Patent:
6,670,698 →
Application:
10/068,717 →
Stacking Structure for Semiconductor Chips and a Semiconductor Package Using It
Patent:
6,982,485 →
Application:
10/076,701 →
Lead-Frame Connector and Circuit Module Assembly
Patent:
7,019,387 →
Application:
10/076,896 →
Stacking Structure for Semiconductor Devices Using a Folded Over Flexible Substrate and Method Therefor
Patent:
7,154,171 →
Application:
10/082,472 →
Thin Semiconductor Package with Semiconductor Chip and Electronic Discrete Device
Patent:
6,576,998 →
Application:
10/086,293 →
Reduced Copper Lead Frame for Saw-Singulated Chip Package
Patent:
6,885,086 →
Application:
10/093,267 →
Low Profile Mounting of Thick Integrated Circuit Packages Within Low-Profile Circuit Modules
Patent:
6,509,637 →
Application:
10/094,731 →
Flip-Chip Micromachine Package Using Seal Layer
Patent:
6,838,309 →
Application:
10/097,905 →
Semiconductor Package and Method for Manufacturing the Same
Semiconductor Package Including Passive Elements and Method of Manufacture
Carrier Frame and Semiconductor Package Including Carrier Frame
Shield Cap and Semiconductor Package Including Shield Cap
Patent:
6,683,795 →
Application:
10/121,215 →
Lead Frame with Plated End Leads and Recesses
Patent:
6,608,366 →
Application:
10/122,598 →
Integrated Circuit Substrate Having Laser-Embedded Conductive Patterns and Method Therefor
Patent:
6,930,256 →
Application:
10/138,225 →
Semiconductor Package Including Isolated Ring Structure
Patent:
6,627,977 →
Application:
10/142,222 →
Laser Module and Optical Subassembly
Patent:
6,807,218 →
Application:
10/144,905 →
Method of Making Near Chip Size Integrated Circuit Package
Semiconductor Package and Method of Making Using Leadframe Having Lead Locks to Secure Leads to Encapsulant
Injection Molded Lens-Barrel Assembly and Method for Fabricating Lens-Barrel and Mount Assemblies
Patent:
6,710,945 →
Application:
10/161,963 →
Semiconductor Package and Method for Manufacturing the Same
Plastic Integrated Circuit Package and Leadframe for Making the Package
Saw and Etch Singulation Method for a Chip Package
Patent:
6,841,414 →
Application:
10/174,603 →
Leadframe Including Corner Leads and Semiconductor Package Using Same
Patent:
6,867,071 →
Application:
10/194,557 →
Semiconductor Package and Method of Manufacturing the Same Which Reduces Warpage
Patent:
7,042,072 →
Application:
10/212,496 →
Integrated Circuit Substrate Having Embedded Wire Conductors and Method Therefor
Patent:
6,831,371 →
Application:
10/223,747 →
Integrated Circuit Having Multiple Power/Ground Connections to a Single External Terminal and Method Therefor
Patent:
6,747,352 →
Application:
10/223,749 →
Method of Making a Semiconductor Package Including Stacked Semiconductor Dies
Optic Semiconductor Module and Manufacturing Method
Optic Semiconductor Package
Patent:
6,646,290 →
Application:
10/227,054 →
Laminated Low-Profile Dual Filter Module for Telecommunications Devices and Method Therefor
Patent:
6,816,032 →
Application:
10/235,135 →
Exposed Lead Qfp Package Fabricated Through the Use of a Partial Saw Process
Patent:
6,818,973 →
Application:
10/237,293 →
Compact Flash Memory Card with Clamshell Leadframe
Patent:
6,919,620 →
Application:
10/245,071 →
Lead-Frame Method and Circuit Module Assembly Including Edge Stiffener
Patent:
6,717,822 →
Application:
10/251,410 →
Semiconductor Device Including Metal Strap Electrically Coupled Between Semiconductor Die and Metal Leadframe
Die Down Multi-Media Card and Method of Making Same
Patent:
6,910,635 →
Application:
10/266,329 →
Wafer-Level Chip-Scale Package
Patent:
6,841,874 →
Application:
10/285,978 →
Image Sensor Package
Wafer Level Package and Fabrication Method
Patent:
6,905,914 →
Application:
10/291,050 →
Semiconductor Package and Method for Fabricating the Same
Integrated Circuit Substrate Having Embedded Passive Comonents and Methods Therefor
Patent:
6,987,661 →
Application:
10/319,022 →
Pre-Molded Leadframe
Patent:
6,798,047 →
Application:
10/329,620 →
Mounting for a Package Containing a Chip
Patent:
6,777,789 →
Application:
10/340,256 →
Integrated Circuit Device Packages and Substrates for Making the Packages
Patent:
6,833,609 →
Application:
10/354,772 →
Method of Making a Semiconductor Package Having Exposed Metal Strap
Reinforced Lead-Frame Assembly for Interconnecting Circuits Within a Circuit Module
Patent:
6,965,159 →
Application:
10/356,997 →
Offset Etched Corner Leads for Semiconductor Package
Patent:
6,847,099 →
Application:
10/358,621 →
Stacking Structure for Semiconductor Devices Using a Folded Over Flexible Substrate and Method Therefor
Patent:
6,879,047 →
Application:
10/370,013 →
Semiconductor Package Capable of Die Stacking
Patent:
6,750,545 →
Application:
10/376,988 →
Semiconductor Package Exhibiting Efficient Lead Placement
Patent:
6,927,483 →
Application:
10/383,504 →
Leadframe Package for Semiconductor Devices
Patent:
6,794,740 →
Application:
10/387,801 →
Integrated Circuit Substrate Having Laminated Laser-Embedded Circuit Layers
Patent:
6,930,257 →
Application:
10/392,738 →
Semiconductor Package Using a Printed Circuit Board and a Method of Manufacturing the Same
Patent:
6,853,060 →
Application:
10/420,977 →
Wire Bonding Method for a Semiconductor Package
Thin Profile Semiconductor Package Which Reduces Warpage and Damage During Laser Markings
Patent:
6,833,619 →
Application:
10/425,134 →
Leadframe Based Memory Card
Patent:
7,095,103 →
Application:
10/427,117 →
Semiconductor Package Including Low Temperature Co-Fired Ceramic Substrate
Patent:
6,879,034 →
Application:
10/427,118 →
Sheet Resin Composition and Process for Manufacturing Semiconductor Device Therewith
Semiconductor Package Having More Reliable Electrical Conductive Patterns
Patent:
6,822,323 →
Application:
10/435,888 →
Color Contacts for a Semiconductor Package
Stackable Semiconductor Package and Method for Manufacturing Same
Leadframe Strip Having Enhanced Testability
Patent:
7,008,825 →
Application:
10/445,754 →
Semiconductor Package with Increased Number of Input and Output Pins
Patent:
6,876,068 →
Application:
10/447,012 →
Fully-Molded Leadframe Stand-Off Feature
Patent:
6,897,550 →
Application:
10/459,097 →
Lead Frame with Plated End Leads
Patent:
7,183,630 →
Application:
10/459,230 →
Semiconductor Package and Method for Fabricating the Same
Electronic Structures Including Conductive Shunt Layers
Integrated Circuit Substrate Having Laser-Exposed Terminals
Patent:
7,028,400 →
Application:
10/603,878 →
Drop Resistant Bumpers for Fully Molded Memory Cards
Patent:
7,485,952 →
Application:
10/607,324 →
Thermally Enhanced Chip Scale Lead on Chip Semiconductor Package and Method of Making Same
Patent:
6,873,032 →
Application:
10/610,016 →
Double Downset Double Dambar Suspended Leadframe
Patent:
6,911,718 →
Application:
10/614,440 →
Power Semiconductor Package with Strap
Patent:
6,873,041 →
Application:
10/618,192 →
Multi-Chip Semiconductor Package with Integral Shield and Antenna
Patent:
7,049,682 →
Application:
10/621,780 →
Circuit Module Having Interconnects for Connecting Functioning and Non-Functioning Add Ons and Method Therefor
Patent:
7,102,891 →
Application:
10/625,290 →
Plastic Integrated Circuit Package and Method and Leadframe for Making the Package
Patent:
7,071,541 →
Application:
10/626,150 →
Semiconductor Memory Card
Patent:
8,258,613 →
Application:
10/634,541 →
Near Chip Size Semiconductor Package
Exposed Lead Interposer Leadframe Package
Patent:
7,245,007 →
Application:
10/667,226 →
Leadframe Having Lead Locks to Secure Leads to Encapsulant
Reinforced Die Pad Support Structure
Semiconductor Package Structure Reducing Warpage and Manufacturing Method Thereof
Patent:
6,936,922 →
Application:
10/672,886 →
Semiconductor Package and Method for Manufacturing the Same
Front Edge Chamfer Feature for Fully-Molded Memory Cards
Patent:
6,998,702 →
Application:
10/680,281 →
Mounting for a Package Containing a Chip
Patent:
6,967,395 →
Application:
10/688,138 →
Method of Making an Integrated Circuit Package
Patent:
6,893,900 →
Application:
10/688,710 →
Stacked Electronic Structures Including Offset Substrates
Semiconductor package including leads and conductive posts for providing increased functionality
Patent:
7,138,707 →
Application:
10/690,193 →
Stackable Semiconductor Package and Manufacturing Method Thereof
Patent:
6,977,431 →
Application:
10/702,274 →
Manufacturing Method for Leadframe and for Semiconductor Package Using the Leadframe
Patent:
7,144,517 →
Application:
10/703,301 →
Stacked Semiconductor Die Assembly Having at Least One Support
Patent:
6,930,378 →
Application:
10/705,194 →
Semiconductor Package with Chamfered Corners and Method of Manufacturing the Same
Patent:
7,211,879 →
Application:
10/706,468 →
Image Sensor Package and Method for Manufacture Thereof
Patent:
7,091,571 →
Application:
10/735,184 →
Semiconductor Package with Exposed Die Pad and Body-Locking Leadframe
Patent:
6,965,157 →
Application:
10/737,572 →
Semiconductor Package with Substrate Coupled to a Peripheral Side Surface of a Semiconductor Die
Patent:
7,009,296 →
Application:
10/759,990 →
Semiconductor Package Having Reduced Thickness
Cavity Case with Clip/Plug for Use on Multi-Media Card
Patent:
7,057,268 →
Application:
10/765,397 →
Leadframe Type Semiconductor Package Having Reduced Inductance and Its Manufacturing Method
Patent:
7,091,594 →
Application:
10/766,046 →
Double Mold Memory Card and Its Manufacturing Method
Patent:
7,633,763 →
Application:
10/766,101 →
Structures for Improving Heat Dissipation in Stacked Semiconductor Packages
Patent:
6,919,631 →
Application:
10/771,072 →
Lead Frame for Semiconductor Package
Methods of Selectively Bumping Integrated Circuit Substrates and Related Structures
Leadframe Package for Semiconductor Devices
Patent:
6,844,615 →
Application:
10/781,220 →
Semiconductor Package and Method for Fabricating the Same
Low Temperature Methods of Bonding Components and Related Structures
Stackable Semiconductor Package Having Semiconductor Chip Within Central Through Hole of Substrate
Method of Manufacturing a Semiconductor Package
Patent:
7,185,426 →
Application:
10/806,640 →
Semiconductor Package and Method for Fabricating the Same
Patent:
40,112 →
Application:
10/825,670 →
Tape Supported Memory Card Leadframe Structure
Patent:
7,074,654 →
Application:
10/828,616 →
Semiconductor Package Having One or More Die Stacked on a Prepackaged Device and Method Therefor
Patent:
6,946,323 →
Application:
10/831,505 →
Electronic Devices Including Metallurgy Structures for Wire and Solder Bonding
Semiconductor Package and Substrate Having Multi-Level Vias
Patent:
7,145,238 →
Application:
10/839,647 →
Method of Making an Integrated Circuit Package
Patent:
7,005,326 →
Application:
10/847,742 →
Semiconductor Device and Its Manufacturing Method
Patent:
7,145,253 →
Application:
10/865,096 →
Embedded Leadframe Semiconductor Package
Patent:
7,190,062 →
Application:
10/868,244 →
Semiconductor Package Having Improved Adhesiveness and Ground Bonding
Methods of Forming Conductive Structures Including Titanium-Tungsten Base Layers and Related Structures
Exposed Lead Qfp Package Fabricated Through the Use of a Partial Saw Process
Patent:
7,211,471 →
Application:
10/881,846 →
Stackable Semiconductor Package with Solder on Pads on Which Second Semiconductor Package Is Stacked
Patent:
6,987,314 →
Application:
10/883,593 →
Substrate for Semiconductor Package and Wire Bonding Method Using Thereof
Semiconductor Package and Method for Manufacturing the Same
Patent:
7,045,893 →
Application:
10/892,625 →
Offset Etched Corner Leads for Semiconductor Package
Patent:
7,598,598 →
Application:
10/910,089 →
Semiconductor Package and Its Manufacturing Method
Patent:
7,202,554 →
Application:
10/921,642 →
Pre-Molded Leadframe
Patent:
7,102,214 →
Application:
10/923,575 →
Image Sensor Package Fabrication Method
Semiconductor Package
Semiconductor Package Including Flip Chip
Method for Making an Integrated Circuit Substrate Having Embedded Back-Side Access Conductors and Vias
Image Sensor Package and Its Manufacturing Method
Patent:
7,359,579 →
Application:
10/962,221 →
Methods of Providing Solder Structures for Out Plane Connections
Memory Card and Its Manufacturing Method
Patent:
7,201,327 →
Application:
10/967,462 →
Fan-In Leadframe Semiconductor Package
Patent:
7,217,991 →
Application:
10/971,408 →
Semiconductor Package Having a Plurality Input/Output Members
Memory Card Esc Substrate Insert
Patent:
7,193,305 →
Application:
10/980,355 →
Integrated Circuit Device Packages and Substrates for Making the Packages
Patent:
7,253,503 →
Application:
10/986,634 →
Interposer for Interconnecting Components in a Memory Card
Patent:
7,358,600 →
Application:
10/990,265 →
Stacked-Die Extension Support Structure and Method Thereof
Patent:
7,071,568 →
Application:
10/991,631 →
Shielded Package Having Shield Fence
Patent:
7,629,674 →
Application:
10/992,036 →
Wafer-Level Chip-Scale Package
Patent:
6,987,319 →
Application:
11/006,210 →
Method of Making a Leadframe for Semiconductor Devices
Patent:
7,001,799 →
Application:
11/009,262 →
Thermally Enhanced Chip Scale Lead on Chip Semiconductor Package and Method of Making Same
Patent:
7,064,009 →
Application:
11/018,731 →
Plastic Integrated Circuit Package and Method and Leadframe for Making the Package
Patent:
7,030,474 →
Application:
11/021,340 →
Method for Making an Integrated Circuit Substrate Having Laser-Embedded Conductive Patterns
Patent:
7,312,103 →
Application:
11/021,977 →
Lead-Frame Method and Assembly for Interconnecting Circuits Within a Circuit Module
Patent:
7,176,062 →
Application:
11/035,239 →
Colored Conductive Wires for a Semiconductor Package
Increased Capacity Leadframe and Semiconductor Package Using the Same
Patent:
7,214,326 →
Application:
11/039,434 →
Two-Sided Wafer Escape Package
Patent:
7,247,523 →
Application:
11/047,848 →
Memory Card and Its Manufacturing Method
Patent:
7,220,915 →
Application:
11/060,263 →
Secure Digital Memory Card Using Land Grid Array Structure
Patent:
7,112,875 →
Application:
11/060,264 →
Semiconductor Package with Increased Number of Input and Output Pins
Methods of Forming Bumps Using Barrier Layers as Etch Masks
Method for Making an Integrated Circuit Substrate Having Embedded Passive Components
Patent:
7,334,326 →
Application:
11/078,833 →
Surface Acoustic Wave (Saw) Device Package and Method for Packaging a Saw Device
Patent:
7,362,038 →
Application:
11/108,359 →
Die Down Multi-Media Card and Method of Making Same
Patent:
7,011,251 →
Application:
11/109,329 →
Die-Mounting Substrate and Method Incorporating Dummy Traces for Improving Mounting Film Planarity
Patent:
7,755,176 →
Application:
11/111,316 →
Image Sensor Package and Its Manufacturing Method
Patent:
7,227,236 →
Application:
11/115,574 →
Wafer Level Chip Scale Package and Manufacturing Method for the Same
Patent:
7,446,422 →
Application:
11/115,579 →
Stacked Die Assembly Having Semiconductor Die Overhanging Support
Patent:
7,132,753 →
Application:
11/115,706 →
Camera Module Having a Threaded Lens Barrel and a Ball Grid Array Connecting Device
Secure Digital Memory Card Using Land Grid Array Structure
Patent:
7,293,716 →
Application:
11/120,087 →
Wafer Level Package and Fabrication Method
Patent:
7,192,807 →
Application:
11/123,605 →
Wafer Level Stacked Package
Patent:
7,170,183 →
Application:
11/128,633 →
Thin Semiconductor Package Including Stacked Dies
Circuit-On-Foil Process for Manufacturing a Laminated Semiconductor Package Substrate Having Embedded Conductive Patterns
Patent:
7,297,562 →
Application:
11/166,005 →
Package in Package (Pip)
Patent:
7,745,918 →
Application:
11/168,168 →
Methods of Forming Lead Free Solder Bumps
Direct Glass Attached on Die Optical Module
Patent:
7,576,401 →
Application:
11/177,904 →
Apparatus and Method for Testing Integrated Circuit Devices Having Contacts on Multiple Surfaces
Patent:
7,385,408 →
Application:
11/180,463 →
Land Patterns for a Semiconductor Stacking Structure and Method Therefor
Patent:
7,429,799 →
Application:
11/190,596 →
Transducer Assembly, Capillary and Wire Bonding Method Using the Same
Thermally Enhanced Chip Scale Lead on Chip Semiconductor Package and Method of Making Same
Patent:
7,045,883 →
Application:
11/198,074 →
Snap Lid Camera Module
Stack Land Grid Array Package and Method for Manufacturing the Same
Patent:
7,408,254 →
Application:
11/212,979 →
Optical Structures Including Liquid Bumps and Related Methods
Methods of Forming Electronic Structures Including Conductive Shunt Layers and Related Structures
Wafer Level Chip Scale Package
Patent:
7,335,986 →
Application:
11/227,410 →
Wire Bonding Machine Capable of Removing Particles from Capillary and Cleaning Method of Capillary Bottom Tip
Method of Forming a Stack of Semiconductor Packages
Patent:
7,459,349 →
Application:
11/254,339 →
Enhanced Durability Memory Card
Patent:
7,375,975 →
Application:
11/263,428 →
Non-Circular via Holes for Bumping Pads and Related Structures
Method for Manufacturing a Semiconductor Device Substrate
Patent:
7,317,245 →
Application:
11/279,002 →
Method of Forming a Stacked Semiconductor Package
Modular Memory Card and Method of Making Same
Patent:
7,837,120 →
Application:
11/288,906 →
Etch Singulated Semiconductor Package
Patent:
7,507,603 →
Application:
11/292,778 →
Semiconductor Package Including a Top-Surface Metal Layer for Implementing Circuit Features
Patent:
7,633,765 →
Application:
11/293,999 →
Stacked Embedded Leadframe
Patent:
7,361,533 →
Application:
11/297,050 →
Embedded Electronic Component Package
Patent:
7,572,681 →
Application:
11/298,016 →
Method of Making an Integrated Circuit Package
Patent:
7,112,474 →
Application:
11/299,859 →
Optical Module Having Cavity Substrate
Patent:
7,609,461 →
Application:
11/315,994 →
Multiple Cover Memory Card
Patent:
7,359,204 →
Application:
11/355,092 →
Stacked Electronic Component Package Having Film-on-Wire Spacer
Patent:
7,675,180 →
Application:
11/356,921 →
Solder Structures for Out of Plane Connections
Semiconductor Device Having Rf Shielding and Method Therefor
Patent:
7,342,303 →
Application:
11/364,427 →
Semiconductor Package and Method of Making Using Leadframe Having Lead Locks to Secure Leads to Encapsulant
Land Patterns for a Semiconductor Stacking Structure and Method Therefor
Patent:
7,652,361 →
Application:
11/367,171 →
Leadframe and Semiconductor Package Made Using the Leadframe
Chamfered Memory Card Module and Method of Making Same
Patent:
7,719,845 →
Application:
11/379,550 →
Semiconductor Package Having Improved Adhesiveness and Ground Bonding
Tape Supported Memory Card Leadframe Structure
Patent:
7,556,986 →
Application:
11/425,502 →
Side Leaded, Bottom Exposed Pad and Bottom Exposed Lead Fusion Quad Flat Semiconductor Package
Patent:
7,968,998 →
Application:
11/425,505 →
Secure Digital Memory Card Using Land Grid Array Structure
Patent:
7,485,491 →
Application:
11/427,454 →
Substrate for Semiconductor Device and Manufacturing Method Thereof
Patent:
7,902,660 →
Application:
11/440,548 →
Semiconductor Package
Patent:
7,633,144 →
Application:
11/440,662 →
Electronic Devices Including Offset Conductive Bumps
Capacitor and Resistor Having Anodic Metal and Anodic Metal Oxide Structure
Patent:
7,755,164 →
Application:
11/472,874 →
Semiconductor Package Having Reduced Thickness
Patent:
7,321,162 →
Application:
11/492,481 →
Buildup Dielectric and Metallization Process and Semiconductor Package
Patent:
7,548,430 →
Application:
11/497,617 →
Method of Making an Integrated Circuit Package
Patent:
7,332,375 →
Application:
11/503,752 →
Lead Frame for Semiconductor Package
Camera Module Fabrication Method Including Singulating a Substrate
Semiconductor Package Substrate Fabrication Method
Patent:
7,501,338 →
Application:
11/527,104 →
Semiconductor Package and Substrate Having Multi-Level Vias Fabrication Method
Patent:
7,365,006 →
Application:
11/527,827 →
Stacked Die Assembly Having Semiconductor Die Projecting Beyond Support
Patent:
7,459,776 →
Application:
11/529,467 →
Embedded Metal Features Structure
Patent:
7,589,398 →
Application:
11/543,540 →
Thermally Enhanced Semiconductor Package
Stacked Redistribution Layer (Rdl) Die Assembly Package
Patent:
7,550,857 →
Application:
11/560,496 →
Membrane Die Attach Circuit Element Package and Method Therefor
Patent:
7,781,852 →
Application:
11/566,731 →
Exposed Die Overmolded Flip Chip Package and Fabrication Method
Patent:
7,898,093 →
Application:
11/592,889 →
Semiconductor Package Including Top-Surface Terminals for Mounting Another Semiconductor Package
Patent:
7,671,457 →
Application:
11/595,411 →
Electronic Component Package Comprising Fan-Out and Fan-in Traces
Patent:
7,714,431 →
Application:
11/605,740 →
Blind via Capture Pad Structure
Patent:
7,750,250 →
Application:
11/615,467 →
Exposed Metal Bezel for Use in Sensor Devices and Method Therefor
Patent:
7,859,116 →
Application:
11/616,069 →
Semiconductor Package Having Leadframe with Exposed Anchor Pads
Method of Fabricating an Embedded Circuit Pattern
Patent:
7,752,752 →
Application:
11/621,402 →
Methods of Forming Back Side Layers for Thinned Wafers
Stackable Semiconductor Package Including Laminate Interposer
Patent:
7,829,990 →
Application:
11/624,648 →
Methods of Forming Metal Layers Using Multi-Layer Lift-Off Patterns
Electronic Devices Including Solder Bumps on Compliant Dielectric Layers
Stackable Semiconductor Package Having Partially Exposed Semiconductor Die and Method of Fabricating the Same
Patent:
7,982,297 →
Application:
11/682,666 →
Method for Fabricating a Fan-in Leadframe Semiconductor Package
Patent:
7,473,584 →
Application:
11/685,072 →
Camera Module Fabrication Method Including the Step of Removing a Lens Mount and Window from the Mold
Semiconductor Package and Fabricating Method Thereof
Patent:
7,808,105 →
Application:
11/734,999 →
A Semiconductor Device Having Emi Shielding and Method Therefor
Patent:
7,898,066 →
Application:
11/754,209 →
Conductive Structures Including Titanium-Tungsten Base Layers
Metal Etch Stop Fabrication Method and Structure
Patent:
7,923,645 →
Application:
11/765,806 →
Embedded Die Metal Etch Stop Fabrication Method and Structure
Patent:
7,951,697 →
Application:
11/765,828 →
Semiconductor Device Having Rf Shielding and Method Therefor
Patent:
7,745,910 →
Application:
11/775,492 →
Fusion Quad Flat Semiconductor Package
Two-Sided Wafer Escape Package
Patent:
7,420,272 →
Application:
11/784,979 →
Direct-Write Wafer Level Chip Scale Package
Semiconductor Device Having a Stacked Bump to Reduce Kirkendall Voids and or Cracks and Method of Manufacturing
Dual Laminate Package Structure with Embedded Elements
Patent:
7,687,899 →
Application:
11/835,235 →
Straight Conductor Blind via Capture Pad Structure and Fabrication Method
Patent:
8,323,771 →
Application:
11/839,277 →
Thin Stacked Interposer Package
Patent:
7,777,351 →
Application:
11/865,617 →
Semiconductor Package with Increased I/O Density and Method of Making the Same
Patent:
8,089,159 →
Application:
11/866,886 →
Wafer Level Package Utilizing Laser-Activated Dielectric Material
Patent:
7,632,753 →
Application:
11/867,293 →
Methods of Forming Electronic Structures Including Conductive Shunt Layers and Related Structures
Structure of Bond Pad for Semiconductor Die and Method Therefor
Patent:
8,198,738 →
Application:
11/873,229 →
Solder Attach Film and Method of Forming Solder Ball Using the Same
Patent:
7,718,523 →
Application:
11/875,597 →
Substrate Having Stiffener Fabrication Method
Embedded Passive Component Network Substrate Fabrication Method
Patent:
7,958,626 →
Application:
11/924,156 →
Semiconductor Package and Fabrication Method Thereof
Patent:
7,919,853 →
Application:
11/933,908 →
Reduced Size Stacked Semiconductor Package and Method of Making the Same
Patent:
7,847,386 →
Application:
11/935,314 →
Thin Substrate Fabrication Method and Structure
Patent:
8,017,436 →
Application:
11/953,680 →
Integrated Circuit Package and Method of Making the Same
Patent:
7,560,804 →
Application:
11/970,712 →
Semiconductor Device Having Rf Shielding and Method Therefor
Patent:
8,299,610 →
Application:
11/971,577 →
Circuit-On-Foil Process for Manufacturing a Laminated Semiconductor Package Substrate Having Embedded Conductive Patterns
Patent:
8,322,030 →
Application:
11/982,637 →
Semiconductor Package with Patterning Layer and Method of Making Same
Patent:
7,956,453 →
Application:
12/015,428 →
Stacked Semiconductor Package and Method of Making Same
Patent:
7,723,852 →
Application:
12/017,266 →
Shielded Trace Structure and Fabrication Method
Patent:
7,832,097 →
Application:
12/018,435 →
Semiconductor Package Having a Land to Absorb Thermal and Mechanical Stress and Fabricating Method Thereof
Patent:
7,982,316 →
Application:
12/025,336 →
Semiconductor Device Having Improved Contact Interface Reliability and Method Therefor
Patent:
8,193,624 →
Application:
12/036,498 →
Methods for Treating or Preventing Metastatic Cancer Using Benzopyranone Compounds
Flat Semiconductor Package with Half Package Molding
Patent:
8,067,821 →
Application:
12/100,886 →
Semiconductor Package with Fast Power-Up Cycle and Method of Making Same
Patent:
7,768,135 →
Application:
12/105,196 →
System and Method to Reduce Shorting of Radio Frequency (Rf) Shielding
Patent:
8,008,753 →
Application:
12/107,478 →
Semiconductor Device Having Reduced Thermal Interface Material (Tim) Degradation and Method Therefor
Patent:
7,906,845 →
Application:
12/108,419 →
Lead Free Alloy Bump Structure and Fabrication Method
Patent:
7,994,043 →
Application:
12/108,909 →
Semiconductor Package with Half-Etched Locking Features
Patent:
7,808,084 →
Application:
12/116,127 →
Semiconductor Device Having Redistribution Layer
Patent:
8,058,726 →
Application:
12/116,695 →
Flip Chip Bump Structure and Fabrication Method
Patent:
7,932,170 →
Application:
12/144,145 →
Multi-Level Circuit Substrate Fabrication Method
Patent:
8,316,536 →
Application:
12/151,857 →
Semiconductor Device Having Improved Contact Interface Reliability and Method Therefor
Patent:
7,944,043 →
Application:
12/169,151 →
Increased I/O Semiconductor Package and Method of Making Same
Patent:
8,125,064 →
Application:
12/181,256 →
Increased Capacity Semiconductor Package
Patent:
8,184,453 →
Application:
12/183,979 →
Land Patterns for a Semiconductor Stacking Structure and Method Therefor
Patent:
7,691,745 →
Application:
12/187,578 →
Semiconductor Package Having Through Holes
Patent:
7,843,072 →
Application:
12/190,039 →
Electronic Structures Including Barrier Layers Defining Lips
Semiconductor Device Having Insulating and Interconnection Layers
Patent:
8,334,590 →
Application:
12/204,692 →
Two-Sided Fan-Out Wafer Escape Package
Patent:
7,692,286 →
Application:
12/221,797 →
Camera Module with Window Mechanical Attachment
Ultra Thin Package and Fabrication Method
Patent:
7,842,541 →
Application:
12/237,173 →
Semiconductor Device Including Leadframe with Increased I/O
Patent:
7,847,392 →
Application:
12/242,603 →
Increased I/O Leadframe and Semiconductor Device Including Same
Patent:
7,989,933 →
Application:
12/246,226 →
Semiconductor Device with Increased I/O Leadframe
Patent:
8,008,758 →
Application:
12/259,096 →
Package Failure Prognostic Structure and Method
Patent:
8,022,521 →
Application:
12/269,357 →
Semiconductor Devices and Fabrication Methods Thereof
Patent:
7,843,052 →
Application:
12/270,690 →
Semiconductor Device Including Increased Capacity Leadframe
Patent:
8,089,145 →
Application:
12/272,606 →
Semiconductor Device with Increased I/O Leadframe Including Passive Device
Patent:
8,072,050 →
Application:
12/273,500 →
Semiconductor Device Including Leadframe Having Power Bars and Increased I/O
Patent:
7,875,963 →
Application:
12/276,121 →
Stackable Semiconductor Package
Patent:
7,737,542 →
Application:
12/291,119 →
Adhesive on Wire Stacked Semiconductor Package
System and Method to Provide Rf Shielding for a Mems Microphone Package
Shielding for a Semiconductor Package
Patent:
8,129,824 →
Application:
12/327,716 →
Package in Package Semiconductor Device
Patent:
7,982,298 →
Application:
12/327,763 →
Package in Package Semiconductor Device with Film Over Wire
Patent:
8,487,420 →
Application:
12/330,424 →
System and Method for Compartmental Shielding of Stacked Packages
Patent:
8,102,032 →
Application:
12/330,769 →
Semiconductor Device Having Emi Shielding and Method Therefor
Patent:
8,012,868 →
Application:
12/335,365 →
Semiconductor Package Having a Heat Spreader with an Exposed Exterior Surface and a Top Mold Gate
Patent:
8,018,072 →
Application:
12/342,386 →
System and Method for Shielding of Package on Package (Pop) Assemblies
Patent:
7,851,894 →
Application:
12/342,829 →
Protruding Post Substrate Package Structure and Method
Patent:
8,176,628 →
Application:
12/342,839 →
Micro-Optical Device Packaging System
Package in Package Device for Rf Transceiver Module
Patent:
8,058,715 →
Application:
12/351,690 →
Etch Singulated Semiconductor Package
Patent:
7,732,899 →
Application:
12/365,682 →
Stacked Redistribution Layer (Rdl) Die Assembly Package
Patent:
7,825,520 →
Application:
12/387,672 →
Buildup Dielectric Layer Having Metallization Pattern Semiconductor Package Fabrication Method
Patent:
8,341,835 →
Application:
12/387,691 →
Reduced Profile Stackable Semiconductor Package
Patent:
8,026,589 →
Application:
12/390,999 →
Semiconductor Device
Patent:
7,872,341 →
Application:
12/396,772 →
Reversible Top/Bottom Mems Package
Patent:
8,030,722 →
Application:
12/397,470 →
Conformal Shield on Punch Qfn Semiconductor Package
Patent:
7,960,818 →
Application:
12/398,089 →
Leadframe for Semiconductor Package
Adhesive Composition for Semiconductor Device
Patent:
8,004,078 →
Application:
12/405,854 →
Fine Pitch Copper Pillar Package and Method
Patent:
8,536,458 →
Application:
12/414,220 →
Thermal via Heat Spreader Package and Method
Patent:
7,960,827 →
Application:
12/421,118 →
Wire Bonder for Improved Bondability of a Conductive Wire and Method Therefor
Patent:
7,938,308 →
Application:
12/429,448 →
Solder Structures Including Barrier Layers with Nickel and/or Copper
Embedded Electronic Component Package Fabrication Method
Patent:
7,977,163 →
Application:
12/459,532 →
Direct Glass Attached on Die Optical Module
Patent:
7,911,017 →
Application:
12/459,536 →
Method and Structure for Creating Embedded Metal Features
Patent:
7,911,037 →
Application:
12/462,665 →
System and Method for Testing Radio Frequency (Rf) Shielding Defects
Patent:
7,839,136 →
Application:
12/481,525 →
Stackable via Package and Method
Patent:
8,222,538 →
Application:
12/483,913 →
System and Method for Rf Shielding of a Semiconductor Package
Patent:
8,093,691 →
Application:
12/502,409 →
Reversible Top/Bottom Mems Package
Patent:
8,115,283 →
Application:
12/502,627 →
Semiconductor Device Having an Interposer
Stackable Variable Height via Package and Method
Patent:
8,471,154 →
Application:
12/537,048 →
Circuit Board and Semiconductor Device Having the Same
Patent:
8,089,148 →
Application:
12/539,116 →
Semiconductor Device with Metal Dam and Fabricating Method
Patent:
8,441,123 →
Application:
12/540,593 →
Semiconductor Device with Electromagnetic Interference Shielding
Semiconductor Device and Fabricating Method Thereof
Patent:
8,183,683 →
Application:
12/549,068 →
Wafer Level Chip Size Package Having Redistribution Layers
Patent:
7,977,783 →
Application:
12/549,083 →
Bumped Chip Package Fabrication Method and Structure
Patent:
7,994,045 →
Application:
12/555,449 →
Shielded Embedded Electronic Component Substrate Fabrication Method and Structure
Patent:
8,432,022 →
Application:
12/569,300 →
Shielded Package Having Shield Lid
Patent:
8,362,597 →
Application:
12/589,500 →
Semiconductor Package Including a Top-Surface Metal Layer for Implementing Circuit Features
Patent:
8,018,068 →
Application:
12/589,839 →
Method of Making Semiconductor Package with Adhering Portion
Patent:
8,129,849 →
Application:
12/589,868 →
Bend Test Method and Apparatus for Flip Chip Devices
Patent:
8,365,611 →
Application:
12/627,484 →
Semiconductor Package Including Top-Surface Terminals for Mounting Another Semiconductor Package
Patent:
8,110,909 →
Application:
12/655,724 →
Stacked Electronic Component Package Having Film-on-Wire Spacer
Patent:
8,072,083 →
Application:
12/657,425 →
Direct-Write Wafer Level Chip Scale Package
Patent:
8,188,584 →
Application:
12/661,597 →
Electronic Component Package Comprising Fan-Out Traces
Patent:
7,932,595 →
Application:
12/661,604 →
Flex Circuit Package and Method
Patent:
8,536,462 →
Application:
12/692,397 →
Edge Mount Semiconductor Package
Patent:
8,217,507 →
Application:
12/692,522 →
Semiconductor Package Having Leadframe with Exposed Anchor Pads
Patent:
8,089,141 →
Application:
12/693,372 →
Dual Laminate Package Structure with Embedded Elements
Patent:
7,872,343 →
Application:
12/699,739 →
Heat Spreader Package and Method
Patent:
7,999,371 →
Application:
12/702,505 →
Top Feature Package and Method
Patent:
8,199,518 →
Application:
12/708,033 →
Pogo Pin Inserting Device for Testing Semiconductor Devices and Method Therefor
Patent:
8,237,460 →
Application:
12/708,385 →
Semiconductor Device and Manufacturing Method Thereof
Patent:
8,362,612 →
Application:
12/728,119 →
Semiconductor Device for Improving Electrical and Mechanical Connectivity of Conductive Pillers and Method Therefor
Patent:
8,294,265 →
Application:
12/751,842 →
Through via Nub Reveal Method and Structure
Patent:
8,324,511 →
Application:
12/754,837 →
Stacked Semiconductor Package and Method of Making Same
Patent:
7,906,855 →
Application:
12/758,583 →
Stackable Treated via Package and Method
Patent:
8,300,423 →
Application:
12/787,238 →
Semiconductor Device and Fabricating Method Thereof
Patent:
8,294,276 →
Application:
12/788,845 →
Conductive Polymer Lid for a Sensor Package and Method Therefor
Patent:
8,354,747 →
Application:
12/791,472 →
Solder Attach Film and Assembly
Patent:
7,859,107 →
Application:
12/798,412 →
Stackable Semiconductor Package
Patent:
7,982,306 →
Application:
12/799,751 →
Semiconductor Package Including Top-Surface Terminals for Mounting Another Semiconductor Package
Patent:
8,026,587 →
Application:
12/802,661 →
System and Method for Lowering Contact Resistance of the Radio Frequency (Rf) Shield to Ground
Patent:
8,508,023 →
Application:
12/817,923 →
Semiconductor Package with Fast Power-Up Cycle and Method of Making Same
Patent:
8,084,868 →
Application:
12/818,446 →
Thin Stacked Interposer Package
Patent:
8,319,338 →
Application:
12/832,202 →
Stackable Plasma Cleaned via Package and Method
Patent:
8,338,229 →
Application:
12/846,973 →
Through via Connected Backside Embedded Circuit Features Structure and Method
Patent:
8,440,554 →
Application:
12/848,820 →
Semiconductor Device Having Through Electrodes Protruding from Dielectric Layer
Patent:
8,487,445 →
Application:
12/898,192 →
Electronic Structures Including Barrier Layers and/or Oxidation Barriers Defining Lips and Related Methods
Semiconductor Device Including Leadframe with Increased I/O
Patent:
8,299,602 →
Application:
12/912,490 →
Mechanical Tape Separation Package and Method
Patent:
8,337,657 →
Application:
12/913,325 →
Stackable Package and Method
Patent:
8,482,134 →
Application:
12/917,185 →
Stacked Redistribution Layer (Rdl) Die Assembly Package
Patent:
8,203,203 →
Application:
12/924,493 →
Adhesive on Wire Stacked Semiconductor Package
Stackable Semiconductor Package
Patent:
8,227,905 →
Application:
12/931,325 →
Exposed Die Overmolded Flip Chip Package Method
Patent:
8,207,022 →
Application:
12/931,326 →
Semiconductor Device and Fabricating Method Thereof
Patent:
8,525,318 →
Application:
12/943,540 →
Electronic Structures Including Conductive Layers Comprising Copper and Having a Thickness of at Least 0.5 Micrometers
Light Emitting Diode (Led) Package and Method
Patent:
8,535,961 →
Application:
12/964,397 →
Dual Laminate Package Structure with Embedded Elements
Patent:
8,283,767 →
Application:
12/964,453 →
Concentrated Photovoltaic Receiver Package with Stacked Internal Support Features
Patent:
8,502,361 →
Application:
12/964,468 →
Semiconductor Device Including Leadframe Having Power Bars and Increased I/O
Patent:
8,188,579 →
Application:
12/965,582 →
Through via Recessed Reveal Structure and Method
Patent:
8,390,130 →
Application:
12/985,888 →
Integrated Circuit Package and Method of Making the Same
Patent:
8,318,287 →
Application:
13/009,690 →
Leadframe for Semiconductor Package
Semiconductor Device Capable of Preventing Dielectric Layer from Cracking
Patent:
8,492,893 →
Application:
13/049,647 →
Wafer Level Package Fabrication Method
Patent:
8,119,455 →
Application:
13/065,296 →
Flip Chip Bump Structure and Fabrication Method
Patent:
8,390,116 →
Application:
13/065,298 →
Metal Etch Stop Fabrication Method and Structure
Patent:
8,383,950 →
Application:
13/066,137 →
Metal Mesh Lid Mems Package and Method
Patent:
8,536,663 →
Application:
13/096,359 →
Micro-Optical Device Packaging System
Side Leaded, Bottom Exposed Pad and Bottom Exposed Lead Fusion Quad Flat Semiconductor Package
Patent:
8,441,110 →
Application:
13/109,845 →
Bumped Chip Package Fabrication Method and Structure
Patent:
8,263,486 →
Application:
13/135,070 →
Heat Spreader Package
Patent:
8,441,120 →
Application:
13/135,091 →
Semiconductor Package Including a Top-Surface Metal Layer for Implementing Circuit Features
Patent:
8,227,338 →
Application:
13/136,457 →
Fusion Quad Flat Semiconductor Package
Patent:
8,304,866 →
Application:
13/151,571 →
Increased I/O Leadframe and Semiconductor Device Including Same
Patent:
8,432,023 →
Application:
13/161,380 →
Semiconductor Package Having a Plurality of Input/Output Members
Patent:
8,525,322 →
Application:
13/286,005 →
Semiconductor Package with Increased I/O Density and Method of Making Same
Patent:
8,227,921 →
Application:
13/290,451 →
Wafer Level Package and Fabrication Method
Patent:
8,298,866 →
Application:
13/358,947 →
Direct-Write Wafer Level Chip Scale Package
Patent:
8,501,543 →
Application:
13/472,961 →
Exposed Die Overmolded Flip Chip Package
Patent:
8,368,194 →
Application:
13/487,713 →
Stackable Semiconductor Package
Patent:
8,466,545 →
Application:
13/528,199 →
Bumped Chip Package
Patent:
8,426,966 →
Application:
13/569,865 →
Semiconductor Device for Improving Electrical and Mechanical Connectivity of Conductive Pillers and Method Therefor
Wafer Level Package and Fabrication Method
Patent:
8,486,764 →
Application:
13/627,815 →
Exposed Die Overmolded Flip Chip Package and Fabrication Method
Patent:
8,476,748 →
Application:
13/665,295 →
Exposed Die Overmolded Flip Chip Package and Fabrication Method
Patent:
8,541,260 →
Application:
13/864,750 →
Using Wayside Signals to Optimize Train Driving Under an Overarching Railway Network Safety System
Imaging Element, Electronic Device, and Information Processing Device
Related Assignments
(2)
Other recorded transfers of the patents in this record — the chain of ownership.