Land patterns for a semiconductor stacking structure and method therefor
View Patent ↗A semiconductor device has a substrate and an encapsulation area on a first surface of the substrate. A first plurality of metal lands is on the first surface of the substrate around a periphery of the encapsulation area. Solder mask covers portions of the first plurality of metal lands closest to the encapsulation area. Remaining portions of the first plurality of metal lands are exposed areas having no solder mask.
1. A semiconductor device comprising:
a substrate;
an encapsulation area on a first surface of the substrate;
a first plurality of metal lands on the first surface of the substrate around a periphery of the encapsulation area; and
solder mask covering portions of the first plurality of metal lands closest to the encapsulation area;
wherein remaining portions of the first plurality of metal lands are exposed areas having no solder mask.
2. A semiconductor device in accordance with claim 1 wherein the substrate is exposed around the first plurality of metal lands having exposed areas having no solder mask opposite the capsulation area.
3. A semiconductor device in accordance with claim 2 further comprising at least one anchor, the at least one anchor coupled to the exposed areas having no solder mask on at least one of the first plurality of metal lands and the substrate.
4. A semiconductor device in accordance with claim 1 further comprising a plurality of corner lands located in each corner of the first surface of the substrate, wherein at least one corner land in each corner of the first surface of the substrate are exposed having no solder mask.
5. A semiconductor device in accordance with claim 4 wherein the substrate is exposed around the at least one corner land exposed having no solder mask.
6. A semiconductor device in accordance with claim 5 further comprising at least one corner anchor, the at least one corner anchor coupled to exposed areas having no solder mask on at least one corner land and the substrate.
7. A semiconductor device in accordance with claim 5 further comprising at least one side anchor, the at least one side anchor coupled to exposed areas having no solder mask on at least one of the second plurality of metal lands and the substrate.
8. A semiconductor device in accordance with claim 1 further comprising a second plurality of metal lands located on an outer periphery of the substrate, wherein at least one of the second plurality of metal lands is exposed having no solder mask.
9. A semiconductor device in accordance with claim 8 wherein the substrate is exposed around the at least one of the second plurality of metal lands that is exposed having no solder mask.
10. A semiconductor device comprising:
a substrate;
an encapsulation area on a first surface of the substrate; and
a first plurality of metal lands on the first surface of the substrate around a periphery of the encapsulation area;
wherein a portion of the first plurality of metal lands closest to the encapsulation area is solder mask defined and remaining portions of the first plurality of metal lands are non-solder mask defined.
11. A semiconductor device in accordance with claim 10 further comprising at least one anchor, the at least one anchor coupled to a non-solder mask defined area of one of the first plurality of metal lands and the substrate.
12. A semiconductor device in accordance with claim 10 further comprising a plurality of corner lands located in each corner of the first surface of the substrate, wherein at least one corner land in each corner of the first surface of the substrate are non-solder mask defined.
13. A semiconductor device in accordance with claim 12 further comprising at least one corner anchor, the at least one corner anchor coupled to the at least one non-solder mask defined corner land and the substrate.
14. A semiconductor device in accordance with claim 10 further comprising a second plurality of metal lands located on an outer periphery of the substrate, wherein at least one of the second plurality of metal lands is non-solder mask defined.
15. A semiconductor device in accordance with claim 14 further comprising at least one side anchor, the at least one side anchor coupled to the at least one of the second plurality of metal lands that are non-solder mask defined.
16. A semiconductor device comprising:
a substrate;
an encapsulation area on a first surface of the substrate;
a first plurality of metal lands on the first surface of the substrate around a periphery of the encapsulation area;
solder mask covering portions of the first plurality of metal lands closest to the encapsulation area, remaining portions of the first plurality of metal lands are exposed areas having no solder mask; and
at least one anchor, the at least one anchor coupled to exposed areas having no solder mask on at least one of the first plurality of metal lands and the substrate;
wherein the substrate is exposed around the first plurality of metal lands having exposed areas having no solder mask opposite the encapsulation area.
17. A semiconductor device in accordance with claim 16 further comprising a plurality of corner lands located in each corner of the first surface of the substrate, wherein at least one corner land in each corner of the first surface of the substrate are exposed having no solder mask.
18. A semiconductor device in accordance with claim 17 further comprising at least one corner anchor, the at least one corner anchor coupled to exposed areas having no solder mask on at least one corner land and the substrate.
19. A semiconductor device in accordance with claim 16 further comprising a second plurality of metal lands located on an outer periphery of the substrate, wherein at least one of the second plurality of metal lands is exposed having no solder mask.
20. A semiconductor device in accordance with claim 19 further comprising at least one side anchor, the at least one side anchor coupled to exposed areas having no solder mask on at least one of the second plurality of metal lands and the substrate.