Wafer level stacked package
View Patent ↗Disclosed are a wafer level stacked package and its manufacturing method. As one example, in such a wafer level stacked package, a first semiconductor die is electrically connected to an upper surface of a substrate and a second semiconductor die is electrically connected to a lower surface of the substrate. That is, with respect to one substrate, semiconductor dies can be stacked on upper and lower surfaces of the substrate. Also, underfill is formed between the respective semiconductor dies and the substrate, thereby enhancing bonding forces between the respective semiconductor dies and the substrate. In addition to stacking the semiconductor dies, packages can be stacked with each other. That is, it is possible to stack a plurality of completed wafer level packages with each other in an up-and-down direction.
1. A wafer level stacked package comprising:
a substrate comprising:
an insulative layer having a first surface, a second surface being opposite to the first surface, and four third surfaces being formed around and substantially perpendicular to the first and second surfaces;
at least an electrically conductive terminal formed on the third surfaces of the insulative layer;
at least a first electrically conductive pattern formed on the first surface of the insulative layer; and
at least a second electrically conductive pattern formed on the second surface of the insulative layer;
a first semiconductor die being connected to the first surface of the insulative layer, wherein the first semiconductor die comprises:
a first surface;
a second surface being opposite to the first surface of the first semiconductor die and formed with at least a bond pad; and
four third surfaces being formed around and substantially perpendicular to the first and second surfaces of the first semiconductor die, wherein each third surface of the first semiconductor die and each corresponding third surface of the insulative layer are substantially coplanar with one another and form the same plane; and
a second semiconductor die being connected to the second surface of the insulative layer, wherein the second semiconductor die comprises:
a first surface;
a second surface being opposite to the first surface of the second semiconductor die and being formed with at least a bond pad; and
four third surfaces being formed around and substantially perpendicular to the first and second surfaces of the second semiconductor die, wherein each third surface of the second semiconductor die and each corresponding third surface of the insulative layer are substantially coplanar with one another and form the same plane.
2. The wafer level stacked package as claimed in claim 1 , wherein at least an electrically conductive bump is interposed between the bond pad and the first electrically conductive pattern.
3. The wafer level stacked package as claimed in claim 1 , wherein at least an electrically conductive bump is interposed between the bond pad and the second electrically conductive pattern.
4. The wafer level stacked package as claimed in claim 1 , wherein the electrically conductive terminal is connected to the first electrically conductive pattern, the second electrically conductive pattern or the first and second electrically conductive patterns.
5. A wafer level stacked package comprising:
a substrate comprising:
an insulative layer having a first surface, a second surface being opposite to the first surface, and four third surfaces being formed around and substantially perpendicular to the first and second surfaces; and
at least an electrically conductive terminal formed on the third surfaces of the insulative layer;
a first semiconductor die being connected to the first surface of the insulative layer, wherein the first semiconductor die comprises:
a first surface;
a second surface being opposite to the first surface of the first semiconductor die and formed with at least a bond pad; and
four third surfaces being formed around and substantially perpendicular to the first and second surfaces of the first semiconductor die, wherein each third surface of the first semiconductor die and each corresponding third surface of the insulative layer are substantially coplanar with one another and form the same plane;
a second semiconductor die being connected to the second surface of the insulative layer, wherein the second semiconductor die comprises:
a first surface;
a second surface being opposite to the first surface of the second semiconductor die and being formed with at least a bond pad; and
four third surfaces being formed around and substantially perpendicular to the first and second surfaces of the second semiconductor die, wherein each third surface of the second semiconductor die and each corresponding third surface of the insulative layer are substantially coplanar with one another and form the same plane; and
an underfill is interposed between the first semiconductor die and the substrate and between the second semiconductor die and the substrate.
6. The wafer level stacked package as claimed in claim 1 , wherein at least one third semiconductor die is further connected to the electrically conductive terminal of the insulative layer by means of an electrically conductive bump.
7. The wafer level stacked package as claimed in claim 1 , wherein a lead extending outwardly by a length is further connected to the electrically conductive terminal of the insulative layer by means of a solder.
8. The wafer level stacked package as claimed in claim 1 , wherein the substrate, the first semiconductor die and the second semiconductor die are coupled to a socket inside of which is formed an electrically conductive pattern, the electrically conductive terminal of the substrate being electrically connected to the electrically conductive pattern of the socket.
9. The wafer level stacked package as claimed in claim 1 , wherein the substrate, the first semiconductor die and the second semiconductor die are coupled to an external board formed with a cavity and a plurality of electrically conductive patterns formed outside of the cavity, wherein the electrically conductive terminal of the substrate is connected to the electrically conductive patterns of the external board by means of solders.
10. The wafer level stacked package as claimed in claim 1 , wherein a flexible circuit board formed with an electrically conductive pattern is further connected to the electrically conductive terminal of the substrate.
11. The wafer level stacked package as claimed in claim 10 , wherein the flexible circuit board covers circumferences of the substrate on four sides.
12. A wafer level stacked package comprising:
first and second wafer level stacked packages each comprising:
a substrate comprising:
an insulative layer having a first surface, a second surface being opposite to the first surface, and four third surfaces being formed around and substantially perpendicular to the first and second surfaces; and
at least an electrically conductive terminal formed on the third surfaces of the insulative layer;
a first semiconductor die being connected to the first surface of the insulative layer, wherein the first semiconductor die comprises:
a first surface;
a second surface being opposite to the first surface of the first semiconductor die and formed with at least a bond pad; and
four third surfaces being formed around and substantially perpendicular to the first and second surfaces of the first semiconductor die, wherein each third surface of the first semiconductor die and each corresponding third surface of the insulative layer are substantially coplanar with one another and form the same plane; and
a second semiconductor die being connected to the second surface of the insulative layer, wherein the second semiconductor die of the second wafer level stacked package is mounted on the first semiconductor die of the first wafer level stacked package, wherein the second semiconductor die comprises:
a first surface;
a second surface being opposite to the first surface of the second semiconductor die and being formed with at least a bond pad; and
four third surfaces being formed around and substantially perpendicular to the first and second surfaces of the second semiconductor die, wherein each third surface of the second semiconductor die and each corresponding third surface of the insulative layer are substantially coplanar with one another and form the same plane.
13. The wafer level stacked package as claimed in claim 12 wherein an adhesive mounts the second semiconductor die of the second wafer level stacked package on the first semiconductor die of the first wafer level stacked package.
14. The wafer level stacked package as claimed in claim 12 wherein an oxide film mounts the second semiconductor die of the second wafer level stacked package on the first semiconductor die of the first wafer level stacked package.
15. The wafer level stacked package as claimed in claim 12 , wherein each substrate further comprises:
at least a first electrically conductive pattern formed on the first surface of the insulative layer; and
at least a second electrically conductive pattern formed on the second surface of the insulative layer.
16. The wafer level stacked package as claimed in claim 12 , wherein the first and second wafer level stacked packages each comprise an underfill interposed between the first semiconductor die and the substrate and between the second semiconductor die and the substrate.
17. A wafer level stacked package comprising:
a substrate comprising:
an insulative layer having a first surface, a second surface being opposite to the first surface, and four third surfaces being formed around and substantially perpendicular to the first and second surfaces;
at least a first electrically conductive pattern formed on the first surface of the insulative layer;
at least a second electrically conductive pattern formed on the second surface of the insulative layer; and
at least an electrically conductive terminal formed on the third surfaces of the insulative layer;
a first semiconductor die being connected to the first surface of the insulative layer, wherein the first semiconductor die comprises:
a first surface;
a second surface being opposite to the first surface of the first semiconductor die and formed with at least a bond pad; and
four third surfaces being formed around and substantially perpendicular to the first and second surfaces of the first semiconductor die, and
wherein at least an electrically conductive bump is interposed between the bond pad and the first electrically conductive pattern; and
a second semiconductor die being connected to the second surface of the insulative layer, wherein the second semiconductor die comprises:
a first surface;
a second surface being opposite to the first surface of the second semiconductor die and being formed with at least a bond pad; and
four third surfaces being formed around and substantially perpendicular to the first and second surfaces of the second semiconductor die,
wherein at least an electrically conductive bump is interposed between the bond pad of the second semiconductor die and the second electrically conductive pattern; and
wherein the areas of the substrate, the first semiconductor die and the second semiconductor die are approximately equal.