Buildup dielectric and metallization process and semiconductor package
View Patent ↗A method of manufacturing a semiconductor package includes mounting and electrically connecting a semiconductor die to a substrate. The semiconductor die and the substrate are encapsulated to form an encapsulation. Via holes are laser-ablated through the encapsulation and conductive material is deposited within the via holes to form vias. A first buildup dielectric layer is formed on the encapsulation. Laser-ablated artifacts are laser-ablated in the first buildup layer. The laser-ablated artifacts in the first buildup layer are filled with a first metal layer to form a first electrically conductive pattern in the first build up layer. The operations of forming a buildup layer, forming laser-ablated artifacts in the buildup layer, and filling the laser-ablated artifacts with an electrically conductive material to form an electrically conductive pattern can be performed any one of a number of times to achieve the desired redistribution.
1. A semiconductor package comprising:
a semiconductor die including bond pads;
a substrate, wherein the semiconductor die is mounted on a top surface of the substrate;
an encapsulation covering the semiconductor die and the top surface of the substrate;
blind vias formed through the encapsulation;
electrically conductive features disposed at the top surface of the encapsulation, the electrically conductive features being connected to the blind vias; and
a first buildup dielectric layer having an electrically conductive pattern formed therein, wherein the electrically conductive pattern is electrically connected to the electrically conductive features, wherein the electrically conductive pattern comprises electrically conductive traces extending entirely through the first buildup dielectric layer and extending in a direction substantially parallel to a top surface of the first buildup dielectric layer.
2. The semiconductor package of claim 1 wherein the first buildup dielectric layer is formed at least on the top surface of the encapsulation.
3. The semiconductor package of claim 2 wherein the encapsulation has sides and the first buildup dielectric layer has sides that are substantially coplanar with the sides of the encapsulation.
4. The semiconductor package of claim 2 wherein the first buildup dielectric layer entirely encloses the encapsulation.
5. The semiconductor package of claim 4 wherein the first buildup dielectric layer comprises sidewalls in contact with sides of the encapsulation.
6. The semiconductor package of claim 5 wherein the sidewalls contact the top surface of the substrate.
7. The semiconductor package of claim 1 wherein the electrically conductive pattern comprises electrically conductive vias formed within the first buildup dielectric layer and extending in a direction substantially perpendicular to the top surface of the first buildup dielectric layer.
8. A semiconductor package comprising:
a semiconductor die including bond pads;
a substrate, wherein the semiconductor die is mounted on a top surface of the substrate;
an encapsulation covering the semiconductor die and the top surface of the substrate;
blind vias formed through the encapsulation, wherein at least some of the blind vias extend to and contact the bond pads of the semiconductor die;
electrically conductive features disposed at the top surface of the encapsulation, the electrically conductive features being connected to the blind vias;
a first buildup dielectric layer having a first electrically conductive pattern formed therein, wherein the first electrically conductive pattern is electrically connected to the electrically conductive features; and
a second buildup dielectric layer having a second electrically conductive pattern formed therein, wherein the second electrically conductive pattern is electrically connected to the first electrically conductive pattern.
9. The semiconductor package of claim 8 wherein the first buildup dielectric layer is formed at least on the top surface of the encapsulation.
10. The semiconductor package of claim 9 wherein sides of the encapsulation, sides of the first buildup dielectric layer, and sides of the second buildup dielectric layer are substantially coplanar with one another.
11. The semiconductor package of claim 8 wherein the first buildup dielectric layer entirely encloses the encapsulation and wherein the second buildup dielectric layer entirely encloses the first buildup dielectric layer.
12. A semiconductor package comprising:
a semiconductor die including bond pads;
a substrate, wherein the semiconductor die is mounted on a top surface of the substrate;
an encapsulation covering the semiconductor die and the top surface of the substrate;
blind vias formed through the encapsulation;
electrically conductive features disposed at the top surface of the encapsulation, the electrically conductive features being connected to the blind vias;
a first buildup dielectric layer having a first electrically conductive pattern formed therein, wherein the first electrically conductive pattern is electrically connected to the electrically conductive features, wherein the first buildup dielectric layer entirely encloses the encapsulation, and wherein the first buildup dielectric layer comprises sidewalls in contact with sides of the encapsulation;
a second buildup dielectric layer having a second electrically conductive pattern formed therein, wherein the second electrically conductive pattern is electrically connected to the first electrically conductive pattern, wherein the second buildup dielectric layer entirely encloses the first buildup dielectric layer, and wherein the second buildup dielectric layer comprises sidewalls in contact with the sidewalls of the first buildup dielectric layer.
13. The semiconductor package of claim 12 wherein the sidewalls of the first buildup dielectric layer and the sidewalls of the second buildup dielectric layer contact the top surface of the substrate.
14. A semiconductor package comprising:
a semiconductor die mounted to a substrate;
wires electrically connecting the semiconductor die to a circuit pattern of the substrate;
an encapsulation encapsulating the semiconductor die, the substrate, and the wires;
laser-ablated via holes through the encapsulation;
vias formed by conductive material deposited within the laser-ablated via holes;
a first buildup dielectric layer formed on the encapsulation;
laser-ablated artifacts formed in the first buildup dielectric layer; and
a first electrically conductive pattern in the first buildup dielectric layer formed by filling the laser-ablated artifacts in the first buildup dielectric layer with a first metal layer.
15. The semiconductor package of claim 14 wherein the first electrically conductive pattern comprises copper.
16. The semiconductor package of claim 14 wherein the first electrically conductive pattern in the first buildup dielectric layer is electrically connected to the vias.
17. The semiconductor package of claim 14 further comprising:
a second buildup dielectric layer formed on the first buildup dielectric layer;
laser-ablated artifacts formed in the second buildup dielectric layer; and
a second electrically conductive pattern in the second buildup dielectric layer formed by filling the laser-ablated artifacts in the second buildup dielectric layer with a second metal layer.
18. The semiconductor package of claim 17 wherein the first buildup dielectric layer entirely encloses the encapsulation and wherein the second buildup dielectric layer entirely encloses the first buildup dielectric layer.
19. The semiconductor package of claim 14 further comprising:
a plurality of buildup dielectric layers;
laser-ablated artifacts in the plurality of buildup dielectric layers; and
electrically conductive patterns in the buildup dielectric layers formed by filling the laser-ablated artifacts in the buildup dielectric layers with metal layers.