Semiconductor device for improving electrical and mechanical connectivity of conductive pillers and method therefor
View Patent ↗A semiconductor device has a semiconductor die having a first surface and a second surface wherein at least one bond pad is formed on the first surface. A passivation layer is formed on the first surface of the semiconductor device, wherein a central area of the at least one bond is exposed. A seed layer is formed on exposed portions of the bond pad and the passivation layer. A conductive pillar is formed on the seed layer. The conductive pillar has a base portion wherein the base portion has a diameter smaller than the seed layer and a stress relief portion extending from a lateral surface of a lower section of the base portion toward distal ends of the seed layer. A solder layer is formed on the conductive pillar.
1. A semiconductor device comprising:
a semiconductor die having a first surface and a second surface, at least one bond pad formed on the first surface;
a passivation layer formed on the first surface of the semiconductor device, wherein a central area of the at least one bond is exposed;
a seed layer formed on exposed portions of the bond pad and the passivation layer;
a conductive pillar formed on the seed layer, the conductive pillar comprising:
a base portion, the base portion having diameter smaller than a maximum diameter of the seed layer; and
a stress relief portion extending from a lateral surface of a lower section of the base portion toward distal ends of the seed layer, wherein the base portion and the stress relief portion are formed of a same material; and
a solder layer formed on the conductive pillar.
2. The semiconductor device of claim 1 , wherein the base portion and the stress relief portion are integrally formed.
3. The semiconductor device of claim 1 , wherein the stress relief portion has a height gradually decreasing from the lateral surface of the lower portion of the base portion toward the distal ends of the seed layer.
4. The semiconductor device of claim 1 , wherein distal ends of the stress relief portion covers the distal ends of the seed layer.
5. The semiconductor device of claim 1 , wherein a length of the stress relief portion extending from the lateral surface of the lower section of the base portion toward the distal ends of the seed layer is in a range of 0.1 μm to 3 μm.
6. The semiconductor device of claim 1 , wherein the conductive pillar is made of at least one of copper (Cu), nickel (Ni), gold (Au), silver (Ag), aluminum (Al), and combinations thereof.
7. The semiconductor device of claim 1 , wherein the solder layer is in contact with a top surface of the base portion.
8. A semiconductor device comprising:
a semiconductor die having a first surface and a second surface, at least one bond pad formed on the first surface;
a passivation layer formed on the first surface of the semiconductor device, wherein a central area of the at least one bond is exposed;
a seed layer formed on exposed portions of the bond pad and the passivation layer;
a conductive pillar formed on the seed layer, the conductive pillar comprising:
a base portion, the base portion having diameter smaller than a maximum diameter of the seed layer; and
means extending from the lateral surface of a lower section of the base portion toward distal ends of the seed layer for reducing stresses generated at ends of contact portions between the conductive pillar and the seed layer, wherein the base portion and the means for reducing stresses are formed of a same material; and
a solder layer formed on the conductive pillar.
9. The semiconductor device of claim 8 , wherein the base portion and the means for reducing stresses are integrally formed.
10. The semiconductor device of claim 8 , wherein the means for reducing stresses has a height gradually decreasing from the lateral surface of the lower portion of the base portion toward the distal ends of the seed layer.
11. The semiconductor device of claim 8 , wherein distal ends of the means for reducing stresses cover the distal ends of the seed layer.
12. The semiconductor device of claim 8 , wherein a length of the means for reducing stresses extend from the lateral surface of the lower section of the base portion toward the distal ends of the seed layer is in a range of 0.1 μm to 3 μm.
13. The semiconductor device of claim 8 , wherein the conductive pillar is made of at least one of copper (Cu), nickel (Ni), gold (Au), silver (Ag), aluminum (Al), and combinations thereof.
14. The semiconductor device of claim 8 , wherein the solder layer is in contact with a top surface of the base portion.
15. A semiconductor device comprising:
a semiconductor die having at least one bond pad formed thereon;
a seed layer formed on exposed portions of the bond pad;
a conductive pillar formed on the seed layer, the conductive pillar comprising:
a base portion, the base portion having diameter smaller than a maximum diameter of the seed layer; and
a stress relief portion extending from a lateral surface of a lower section of the base portion toward distal ends of the seed layer, wherein the base portion and the stress relief portion are formed of a same material; and
a solder layer formed on the conductive pillar.
16. The semiconductor device of claim 15 further comprising a passivation layer formed on the semiconductor device, wherein a central area of the at least one bond is exposed.
17. The semiconductor device of claim 15 , wherein the base portion and the stress relief portion are integrally formed.
18. The semiconductor device of claim 15 , wherein the stress relief portion has a height gradually decreasing from the lateral surface of the lower portion of the base portion toward the distal ends of the seed layer.
19. The semiconductor device of claim 15 , wherein distal ends of the stress relief portion covers the distal ends of the seed layer.
20. The semiconductor device of claim 15 , wherein the solder layer is in contact with a top surface of the base portion.